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CY8C21534B-24PVXI PDF预览

CY8C21534B-24PVXI

更新时间: 2024-11-06 09:45:51
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赛普拉斯 - CYPRESS /
页数 文件大小 规格书
47页 1280K
描述
PSoC Programmable System-on-Chip Low power at high speed

CY8C21534B-24PVXI 数据手册

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CY8C21634B, CY8C21534B, CY8C21434B  
CY8C21334B, CY8C21234B  
PSoC® Programmable System-on-Chip™  
SmartSense™ Auto-Tuning user module:  
SmartSense Auto-Tuning is easy to use and provides robust  
noise immunity.  
SmartSense tunes your CapSense system automatically at  
power up and monitors the system in real time to maintain  
optimum performance.  
SmartSense significantly reduces design cycle time by  
eliminating the tuning process from prototype to mass  
production.  
Features  
Powerful Harvard-architecture processor  
M8C processor speeds up to 24 MHz  
Low power at high speed  
Operating voltage: 2.4 V to 5.25 V  
Operating voltages down to 1.0 V using on-chip switch mode  
pump (SMP)  
Industrial temperature range: –40 °C to +85 °C  
Advanced peripherals (PSoC® blocks)  
Four analog Type E PSoC blocks provide:  
• Two comparators with digital-to-analog converter (DAC)  
references  
SmartSense allows maximum production flexibility by  
compensating for variations caused by using multiple  
manufacturing sites and vendors.  
Versatile analog mux  
Common internal analog bus  
• Single or dual 10-bit 28 channel analog-to-digital  
converters (ADC)  
Simultaneous connection of I/O combinations  
Capacitive sensing application capability  
Four digital PSoC blocks provide:  
• 8- to 32-bit timers, counters, and pulse width modulators  
(PWMs)  
• Cyclical redundancy check (CRC) and pseudo random  
sequence (PRS) modules  
Additional system resources  
I2C master, slave, and multi-master to 400 kHz  
Watchdog and sleep timers  
User-configurable low-voltage detection (LVD)  
Integrated supervisory circuit  
On-chip precision voltage reference  
• Full-duplex universal asynchronous receiver transmitter  
(UART), serial peripheral interface (SPI) master or slave  
• Connectable to all general purpose I/O (GPIO) pins  
Complex peripherals by combining blocks  
Logic Block Diagram  
Flexible on-chip memory  
8 KB flash program storage 50,000 erase/write cycles  
512 bytes static random access memory (SRAM) data  
storage  
In-system serial programming (ISSP)  
Partial flash updates  
Flexible protection modes  
EEPROM emulation in flash  
Complete development tools  
Free development software  
(PSoC Designer™)  
Full-featured, in-circuit emulator (ICE) and programmer  
Full-speed emulation  
Complex breakpoint structure  
128-KB trace memory  
Precision, programmable clocking  
Internal ±2.5% 24- / 48-MHz main oscillator  
Internal oscillator for watchdog and sleep  
Programmable pin configurations  
25-mA sink, 10-mA source on all GPIOs  
Pull-up, pull-down, high Z, strong, or open-drain drive modes  
on all GPIOs  
Up to eight analog inputs on GPIOs  
Configurable interrupt on all GPIOs  
Cypress Semiconductor Corporation  
Document Number: 001-67345 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 13, 2011  
[+] Feedback  

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