CY7C924ADX
Pin Descriptions
CY7C924ADX HOTLink Transceiver
Pin
Number
Name
I/O Characteristics
Signal Description
Transmit Path Signals
44, 42, TXDATA[7:0]
TTL input, sampled Parallel Transmit Data Input. Bus width can be configured to accept either
40, 36,
34, 32,
30, 22
on TXCLK↑ or
8 or 10 bit characters. When the encoder is bypassed (ENCBYP* is LOW),
TXDATA[7:0] functions as the least significant eight bits of the 10 or 12 bit
preencoded transmit character.
REFCLK↑,
Internal Pull Up
46
TXINT/
TXDATA[8]
TTL input, sampled Transmit Interrupt Input. This input is only interpreted if both the Transmit
on TXCLK↑ or
FIFO and encoder are enabled (FIFOBYP* and ENCBYP* are HIGH). Any
state change (0→1 or 1→0) in TXINT, forces a character into the transmit
encoder and shifter before accessing the next Transmit FIFO contents. This
signal passes around, not through, the Transmit FIFO.
REFCLK↑,
Internal Pull Up
When TXINT transitions from 0→1, a C0.0 (K28.0) special code is sent. When
TXINT transitions from 1→0, a C3.0 (K28.3) special code is sent. These
special codes force a similar signal transition on the RXINT output of an
attached CY7C924ADX HOTLink Transceiver.
When the Transmit FIFO is bypassed and the encoder is enabled (FIFOBYP*
is LOW and ENCBYP* is HIGH), this input is ignored.
When the Transmit FIFO is bypassed and the encoder is bypassed
(FIFOBYP* and ENCBYP* are LOW), TXDATA[8] functions as the 9th bit of
the 10 or 12 bit preencoded transmit character.
54
TXHALT*/
TXDATA[9]
TTL input, sampled Transmit FIFO Halt Immediate Input. When the Transmit FIFO and the
on TXCLK↑ or
encoder are enabled (FIFOBYP* and ENCBYP* are HIGH) and TXHALT*
asserts LOW, data transmission from the FIFO is suspended and the HOTLink
transmits idle characters (K28.5). During this time, data can still be loaded into
the FIFO. When TXHALT* is deasserted HIGH, normal data processing
proceeds.
REFCLK↑,
Internal Pull Up
When the encoder is bypassed (ENCBYP* is LOW), TXDATA[9] always
functions as the tenth bit of the 10 or 12 bit preencoded transmit character.
When the Transmit FIFO is bypassed and the encoder is enabled (FIFOBYP*
is LOW and ENCBYP* is HIGH), this input is ignored
56
TXSVS/
TXDATA[10]
TTL input, sampled Transmit Send Violation Symbol Input. When the encoder is enabled and
on TXCLK↑ or
the Transmit FIFO is enabled (ENCBYP* and FIFOBYP* are HIGH), this input
is interpreted along with TXSOC and TXSC/D* (see Table 2 on page 15 for
details). When the Transmit FIFO is disabled (FIFOBYP* is LOW) and the
TXSVS bit is set, the character on the TXDATA is ignoredand a C0.7 exception
is sent instead.
REFCLK↑,
Internal Pull Up
When the encoder is bypassed and in 10 bit mode (ENCBYP* and BYTE8/10*
are LOW), TXDATA[10] functions as the eleventh bit of the 12 bit preencoded
transmit character.
When the Encoder is bypassed and in 8 bit mode (ENCBYP* is LOW and
BYTE8/10* is HIGH), this input is ignored.
58
TXSOC/
TXDATA[11]
TTL input, sampled Transmit Start of Cell Input. When the Transmit FIFO and encoder are
on TXCLK↑ or
enabled (ENCBYP* and FIFOBYP* are HIGH), this input is a message frame
delimiter that indicates the beginning of a data packet. It is interpreted along
with TXSVS and TXSC/D* (see Table 2 for details).
REFCLK↑,
Internal Pull Up
When the Transmit FIFO is bypassed (FIFOBYP* is LOW) and the encoder is
enabled (ENCBYP* is HIGH) this input is ignored.
When in 12 bit encoder bypass mode (ENCBYP* and BYTE8/10* are LOW),
TXDATA[11] functions as the twelfth bit (MSB) of the 12 bit preencoded
transmit character.
When the encoder is bypassed and in 8 bit mode (ENCBYP* is LOW and
BYTE8/10* is HIGH), this input is ignored.
Document #: 38-02008 Rev. *E
Page 4 of 58
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