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CY7C68013-100AXC PDF预览

CY7C68013-100AXC

更新时间: 2024-11-23 23:13:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器
页数 文件大小 规格书
48页 1788K
描述
EZ-USB FX2? USB Microcontroller

CY7C68013-100AXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP,
针数:100Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.47
具有ADC:NO地址总线宽度:
位大小:8最大时钟频率:24 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:R-PQFP-G100
JESD-609代码:e4长度:20 mm
湿度敏感等级:3I/O 线路数量:40
端子数量:100最高工作温度:70 °C
最低工作温度:PWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm速度:48 MHz
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER

CY7C68013-100AXC 数据手册

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CY7C68013  
EZ-USB FX2™ USB Microcontroller  
• Supports bus-powered applications by using renumer-  
ation  
1.0  
EZ-USB FX2Features  
• 3.3V operation  
• Single-chip integrated USB 2.0 Transceiver, SIE, and  
Enhanced 8051 Microprocessor  
• Smart Serial Interface Engine  
• Vectored USB interrupts  
• Software: 8051 code runs from:  
Internal RAM, which is downloaded via USB  
Internal RAM, which is loaded from EEPROM  
— External memory device (128 pin package  
• Separate data buffers forthe SETUP and DATA portions  
of a CONTROL transfer  
2
• Integrated I C-compatible controller, runs at 100 or 400  
kHz  
• Four programmable BULK/INTERRUPT/  
ISOCHRONOUS endpoints  
• 48-MHz, 24-MHz, or 12-MHz 8051 operation  
• Four integrated FIFOs  
— Buffering options: double, triple and quad  
• 8- or 16-bit external data interface  
• GPIF  
— Brings glue and FIFOs inside for lower system cost  
— Automatic conversion to and from 16-bit buses  
— Master or slave operation  
— Allows direct connection to most parallel interface  
— FIFOs can use externally supplied clock or asyn-  
chronous strobes  
— Programmable waveform descriptors and configu-  
ration registers to define waveforms  
— Easy interface to ASIC and DSP ICs  
Special autovectors for FIFO and GPIF interrupts  
• Up to 40 general-purpose I/Os  
— Supports multiple Ready (RDY) inputs and Control  
(CTL) outputs  
Integrated, industry standard enhanced 8051:  
— Up to 48-MHz clock rate  
• Four package options—128-pin TQFP, 100-pin TQFP,  
56-pin QFN and 56-pin SSOP  
— Four clocks per instruction cycle  
— Two USARTS  
• Four packages are defined for the family: 56 SSOP, 56  
QFN, 100 TQFP, and 128 TQFP  
— Three counter/timers  
— Expanded interrupt system  
— Two data pointers  
High-performance micro  
using standard tools  
24-MHz  
Ext. XTAL  
with lower-power options  
FX2  
I2C  
Compatible  
Master  
/0.5  
8051 Core  
x20  
/1.0  
/2.0  
VCC  
12/24/48 MHz,  
four clocks/cycle  
PLL  
Abundant I/O  
including two USARTS  
Additional I/Os (24)  
1.5k  
connected for  
full speed  
General  
ADDR (9)  
programmable I/F  
to ASIC/DSP or bus  
standards such as  
D+  
D–  
GPIF  
USB  
2.0  
XCVR  
CY  
Smart  
USB  
8.5 kB  
RAM  
RDY (6)  
CTL (6)  
ATAPI, EPP, etc.  
1.1/2.0  
Engine  
Integrated  
full- and high-speed  
XCVR  
Up to 96 MBytes/s  
burst rate  
4 kB  
FIFO  
8/16  
Enhanced USB core  
Simplifies 8051 core  
“Soft Configuration”  
Easy firmware changes  
FIFO and endpoint memory  
(master or slave operation)  
Figure 1-1. Block Diagram  
Cypress Semiconductor Corporation  
Document #: 38-08012 Rev. *E  
3901 North First Street  
San Jose,CA 95134  
408-943-2600  
Revised February 8, 2005  

CY7C68013-100AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C68013-100AC CYPRESS

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