Datasheet > CY7C68003

CY7C68003

更新时间： 2024-11-29 06:51:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
5页	154K
描述
MoBL-USB TX2UL USB 2.0 ULPI Transceiver

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中文翻译

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数据手册

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CY7C68003 数据手册

DATA BRIEF

CY7C68003

MoBL-USB™ TX2UL USB 2.0

ULPI Transceiver

■ UART Pass Through Mode

■ ESD Compliance:

❐ JESD22-A114D 8 kV Contact Human Body Model (HBM) for

DP, DM, and VSS Pins

❐ IEC61000-4-2 8 kV Contact Discharge

❐ IEC61000-4-2 15 kV Air Discharge

Features

The Cypress MoBL-USB^™TX2UL is a low voltage high speed

(HS) USB 2.0 ULPI Transceiver.

The TX2UL is specifically designed for mobile handset

applications by offering tiny package options and low power

consumption.

■ Support for Industrial Temperature Range (-40°C to 85°C)

■ USB 2.0 Full Speed and High Speed Compliant Transceiver

■ Multi-Range (1.8V to 3.3V) IO Voltages

■ Fully Compliant ULPI Link Interface

■ 8-bit SDR ULPI Data Path

■ Low Power Consumption for Mobile Applications:

❐ 5 uA Nominal Sleep Mode

❐ 30 mA Nominal Active HS Transfer

■ Small Package for Mobile Applications:

❐ 2.14 x 1.76 mm 20-pin WLCSP 0.4 mm Pitch

❐ 4 x 4 mm 24-pin QFN

■ UTMI+ Level 0 Support

■ Integrated Oscillator

Applications

■ Integrated PLL (13, 19.2, 24, or 26 MHz Reference)

■ Integrated USB Pull Up and Termination Resistors

■ 3.0V to 5.775V VBATT Input

■ Mobile Phones

■ PDAs

■ Portable Media Players (PMPs)

■ DTV Applications

■ Portable GPS Units

■ Chip Select Pin

■ Single Ended Device RESET Input

TX2UL Block Diagram

TX2UL

ULPI Block

CLOCK

Control/

Data

Operational

mode

tracking

interrupt

DATA[7:0]

Tx/Rx

Core

DIR

USB

Logic

UTMI+

FS/HS

Level0

PHY

STP

Registers

Block

NXT

ULPI Wrapper

RXD

TXD

Global Control Block

Reset / Clock / Power /

Misc. Control

RESET_N

CS_N

3.3V Regulator

Block

VBATT

(3.0 –

5.775V)

VCC

(1.8V)

POR

1.8V

Bandgap

PLL

13/19.2/

24/26 MHz

XOSC

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 1, 2009

12 3 4 5

中文翻译

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