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CY7C63743C PDF预览

CY7C63743C

更新时间: 2024-11-11 00:04:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 控制器
页数 文件大小 规格书
49页 1948K
描述
enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller

CY7C63743C 数据手册

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CY7C63722C  
CY7C63723C  
CY7C63743C  
enCoRe™ USB Combination Low-Speed  
USB and PS/2 Peripheral Controller  
I/O ports  
1.0  
Features  
— Up to 16 versatile GPIO pins, individually  
• enCoRe™ USB - enhanced Component Reduction  
configurable  
— Internaloscillatoreliminatestheneedforanexternal  
crystal or resonator  
High current drive on any GPIO pin: 50 mA/pin  
current sink  
— Interface can auto-configure to operate as PS/2 or  
USB without the need for external components to  
switch between modes (no General Purpose I/O  
[GPIO] pins needed to manage dual mode capability)  
— Each GPIO pin supports high-impedance inputs,  
internal pull-ups, open drain outputs or traditional  
CMOS outputs  
Maskable interrupts on all I/O pins  
• SPI serial communication block  
— Master or slave operation  
Internal 3.3V regulator for USB pull-up resistor  
Configurable GPIO for real-world interface without  
external components  
— 2 Mbit/s transfers  
• Flexible, cost-effective solution for applications that  
combine PS/2 and low-speed USB, such as mice, game-  
pads, joysticks, and many others.  
• USB Specification Compliance  
Conforms to USB Specification, Version 2.0  
— Conforms to USB HID Specification, Version 1.1  
• Four 8-bit Input Capture registers  
— Two registers each for two input pins  
— Capture timer setting with five prescaler settings  
Separate registers for rising and falling edge capture  
— Simplifies interface to RF inputs for wireless  
applications  
— Supports one low-speed USB device address and  
three data endpoints  
• Internal low-power wake-up timer during suspend  
mode  
— Integrated USB transceiver  
3.3V regulated output for USB pull-up resistor  
• 8-bit RISC microcontroller  
— Periodic wake-up with no external components  
• Optional 6-MHz internal oscillator mode  
Allows fast start-up from suspend mode  
• Watchdog Reset (WDR)  
Harvard architecture  
— 6-MHz external ceramic resonator or internal clock  
mode  
• Low-voltage Reset at 3.75V  
— 12-MHz internal CPU clock  
Internal memory  
• Internal brown-out reset for suspend mode  
• Improved output drivers to reduce EMI  
• Operating voltage from 4.0V to 5.5VDC  
• Operating temperature from 0°C to 70°C  
• CY7C63723C available in 18-pin SOIC, 18-pin PDIP  
• CY7C63743C available in 24-pin SOIC, 24-pin PDIP,  
24-pin QSOP  
• CY7C63722C available in DIE form  
— 256 bytes of RAM  
—8 Kbytes of EPROM  
— Interface can auto-configure to operate as PS/2 or  
USB  
— No external components for switching between PS/2  
and USB modes  
• Industry standard programmer support  
No GPIO pins needed to manage dual mode  
capability  
Cypress Semiconductor Corporation  
Document #: 38-08022 Rev. *C  
198 Champion Court  
San Jose  
CA 95134  
408-943-2600  
Revised February 25, 2006  

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