Datasheet > CY7C4292V-10ASXC

CY7C4292V-10ASXC

更新时间： 2024-11-05 20:53:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
15页	213K
描述
FIFO, 128KX9, 8ns, Synchronous, CMOS, PQFP64

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技术参数
数据手册

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CY7C4292V-10ASXC 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.81
最长访问时间：	8 ns	最大时钟频率 (fCLK)：	100 MHz
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e3
内存密度：	1179648 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	9	湿度敏感等级：	3
端子数量：	64	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	128KX9	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP64,.47SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	3.3 V	认证状态：	Not Qualified
最大待机电流：	0.006 A	子类别：	FIFOs
最大压摆率：	0.025 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	Base Number Matches：	1

CY7C4292V-10ASXC 数据手册

CY7C4282V

CY7C4292V

64K/128K x 9 Low-Voltage Deep Sync FIFOs

with Retransmit and Depth Expansion

Features

Functional Description

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• High-speed, low-power, first-in first-out (FIFO)

memories

• 64K × 9 (CY7C4282V)

• 128K × 9 (CY7C4292V)

The CY7C4282V/92V are high-speed, low-power, FIFO

memories with clocked read and write interfaces. All devices

are nine bits wide. The CY7C4282V/92V can be cascaded to

increase FIFO depth. Programmable features include Almost

Full/Almost Empty flags. These FIFOs provide solutions for a

wide variety of data buffering needs, including high-speed data

acquisition, multiprocessor interfaces, video and communica-

tions buffering.

• 0.35 micron CMOS for optimum speed/power

• High-speed, Near-Zero Latency (True Dual-Ported

Memory Cell), 100-MHz operation (10 ns read/write

cycle times)

• Low power

— I_CC= 25 mA

— I_SB= 6 mA

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and a Write

Enable pin (WEN).

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, and Programmable Almost Empty and

Almost Full status flags

• Retransmit function

• Output Enable (OE) pin

Depth expansion is possible using the Cascade Input (XI),

Cascade Output (XO), and First Load (FL) pins. The XO pin is

connected to the XI pin of the next device, and the XO pin of

the last device should be connected to the XI pin of the first

device. The FL pin of the first device is tied to VSS and the FL

pin of all the remaining devices should be tied to VCC

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability through token-passing

scheme (no external logic required)

• 64-pin 10 × 10 STQFP

• Pin-compatible 3.3V solution for CY7C4282/92

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running Read

Clock (RCLK) and a Read Enable pin (REN). In addition, the

CY7C4282V/92V have an Output Enable pin (OE). The read

and write clocks may be tied together for single-clock

operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies up to

67 MHz are achievable.

0–8

Logic

Diagram

Block

INPUT

WCLK WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

PAE

Dual Port

RAM Array

PAF/XO

64K x 9

128K x 9

WRITE

POINTER

READ

POINTER

RESET

LOGIC

THREE-STATE

OUTPUT REGISTER

FL/RT

XI/LD

READ

CONTROL

EXPANSION

LOGIC

PAF/XO

0 −

RCLK REN

Cypress Semiconductor Corporation

Document #: 38-06014 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 22, 2003

12 3 4 5 6 7...15

中文翻译

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与CY7C4292V-10ASXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C4292V-15ASC	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4292V-15ASCT	CYPRESS	获取价格	暂无描述
CY7C4292V-15ASI	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C4292V-25ASC	CYPRESS	获取价格	64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
CY7C429-30AC	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, PQFP32, PLASTIC, TQFP-32
CY7C429-30AC	ROCHESTER	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, PQFP32, PLASTIC, TQFP-32
CY7C429-30DC	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERDIP-28
CY7C429-30DC	ROCHESTER	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERDIP-28
CY7C429-30DI	CYPRESS	获取价格	FIFO, 2KX9, 30ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERDIP-28
CY7C429-30DMB	CYPRESS	获取价格	256/512/1K/2K/4K x 9 Asynchronous FIFO

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