Datasheet > CY7C4265

CY7C4265

更新时间： 2024-11-10 22:01:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
20页	425K
描述
8K/16Kx18 Deep Sync FIFOs

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中文翻译

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数据手册

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CY7C4265 数据手册

1CY7C4265

fax id: 5413

CY7C4255

CY7C4265

PRELIMINARY

8K/16Kx18 Deep Sync FIFOs

are 18 bits wide and are pin/functionally compatible to the

CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can

be cascaded to increase FIFO depth. Programmable features

include Almost Full/Almost Empty flags. These FIFOs provide

solutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, and commu-

nications buffering.

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

• 8K x 18 (CY7C4255)

• 16K x 18 (CY7C4265)

• 0.5 micron CMOS for optimum speed/power

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

• High-speed 100-MHz operation (10 ns read/write cycle

times)

• Low power — I =45 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, HalfFull, and programmable Almost Empty

and Almost Full status flags

• TTL compatible

• Retransmit function

When WEN is asserted, data is written into the FIFO on the rising

edge of the WCLK signal. While WEN is held active, data is continu-

ally written into the FIFO on each cycle. The output port is controlled

in a similar manner by a free-running read clock (RCLK) and a read

enable pin (REN). In addition, the CY7C4255/65 have an output

enable pin (OE). The read and write clocks may be tied together for

single-clock operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies up to 100

MHz are achievable.

• Output Enable (OE) pins

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Depth Expansion Capability

• 64-pin PLCC and 64-pin TQFP

• Pin-compatible density upgrade to CY7C42X5 family

• Pin-compatible density upgrade to

IDT72205/15/25/35/45

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of the

next device, and the WXO and RXO pins of the last device should be

connected to the WXI and RXI pins of the first device. The FL pin of

the first device is tied to V and the FL pin of all the remaining devic-

Functional Description

es should be tied to V

The CY7C4255/65 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

0 – 17

Logic Block Diagram

INPUT

WCLK

WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

RAM

PAE

PAF

ARRAY

8K x 18

16K x 18

SMODE

WRITE

READ

POINTER

RESET

LOGIC

FL/RT

THREE–STATE

OUTPUTREGISTER

READ

CONTROL

WXI

WXO/HF

RXI

EXPANSION

LOGIC

0 – 17

RXO

4255–1

RCLK

REN

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

July 1995 – Revised November 1996

12 3 4 5 6 7...20

中文翻译

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与CY7C4265相关器件

型号	品牌	获取价格	描述	数据表
CY7C4265-10	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-10AC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-10AI	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-10ASC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-10ASXC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-10AXI	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-10JCR	CYPRESS	获取价格	FIFO, 16KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-10JI	CYPRESS	获取价格	FIFO, 16KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-10JIR	CYPRESS	获取价格	FIFO, 16KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-10JIT	CYPRESS	获取价格	FIFO, 16KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68

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