Datasheet > 存储 > FIFO> CY7C4265-10JCR

CY7C4265-10JCR

更新时间： 2024-11-11 13:07:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
22页	351K
描述
FIFO, 16KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68

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技术参数
数据手册

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CY7C4265-10JCR 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	68
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.8
其他特性：	RETRANSMIT	周期时间：	10 ns
JESD-30 代码：	S-PQCC-J68	长度：	24.2316 mm
内存密度：	294912 bit	内存宽度：	18
功能数量：	1	端子数量：	68
字数：	16384 words	字数代码：	16000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	16KX18
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	24.2316 mm	Base Number Matches：	1

CY7C4265-10JCR 数据手册

CY7C4255

CY7C4265

8K/16K x 18 Deep Sync FIFOs

are 18 bits wide and are pin/functionally compatible to the

CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can

be cascaded to increase FIFO depth. Programmable features

include Almost Full/Almost Empty flags. These FIFOs provide

solutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, and commu-

nications buffering.

Features

• High-speed, low-power, first-in first-out (FIFO)

memories

• 8K x 18 (CY7C4255)

• 16K x 18 (CY7C4265)

• 0.5 micron CMOS for optimum speed/power

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

controlled by a Free-Running Clock (WCLK) and a Write En-

able pin (WEN).

• High-speed 100-MHz operation (10-ns read/write cycle

times)

• Low power — I_CC= 45 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, HalfFull, andprogrammableAlmostEmpty

and Almost Full status flags

• TTL compatible

• Retransmit function

• Output Enable (OE) pins

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

When WEN is asserted, data is written into the FIFO on the rising

edge of the WCLK signal. While WEN is held active, data is continu-

ally written into the FIFO on each cycle. The output port is controlled

in a similar manner by a free-runningRead Clock (RCLK) anda Read

Enable pin (REN). In addition, the CY7C4255/65 have an Output

Enable pin (OE). The read and write clocks may be tied together for

single-clock operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies up to 100

MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Depth Expansion Capability

• 64-pin TQFP and 64-pin STQFP

• Pin-compatible density upgrade to CY7C42X5 family

• Pin-compatible density upgrade to

IDT72205/15/25/35/45

Depth expansion is possible using the Cascade Input (WXI,

RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of the

next device, and the WXO and RXO pins of the last device should be

connected to the WXI and RXI pins of the first device. The FL pin of

the first device is tied to V_SSand the FL pin of all the remaining devic-

Functional Description

es should be tied to V_CC

The CY7C4255/65 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

0 – 17

Logic Block Diagram

INPUT

WCLK

WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

RAM

PAE

PAF

ARRAY

8K x 18

16K x 18

SMODE

WRITE

READ

POINTER

RESET

LOGIC

FL/RT

THREE–STATE

OUTPUTREGISTER

READ

CONTROL

WXI

WXO/HF

RXI

EXPANSION

LOGIC

0 – 17

RXO

4255–1

RCLK

REN

Cypress Semiconductor Corporation

Document #: 38-06004 Rev. *B

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised August 11, 2004

12 3 4 5 6 7...22

中文翻译

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与CY7C4265-10JCR相关器件

型号	品牌	获取价格	描述	数据表
CY7C4265-10JI	CYPRESS	获取价格	FIFO, 16KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-10JIR	CYPRESS	获取价格	FIFO, 16KX18, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-10JIT	CYPRESS	获取价格	FIFO, 16KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4265-15	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-15AC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-15ACT	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-6
CY7C4265-15AI	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-6
CY7C4265-15ASC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-15AXC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4265-15JC	CYPRESS	获取价格	FIFO, 16KX18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68

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