Datasheet > CY7C4255_05

CY7C4255_05

更新时间： 2024-09-24 05:09:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
22页	542K
描述
8K/16K x 18 Deep Sync FIFOs

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中文翻译

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CY7C4255_05 数据手册

CY7C4255

CY7C4265

8K/16K x 18 Deep Sync FIFOs

• Pb-Free Packages Available

Features

Functional Description

• High-speed, low-power, first-in first-out (FIFO)

memories

The CY7C4255/65 are high-speed, low-power, first-in first-out

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide and are pin/functionally compatible to the

CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can

be cascaded to increase FIFO depth. Programmable features

include Almost Full/Almost Empty flags. These FIFOs provide

solutions for a wide variety of data buffering needs, including

high-speed data acquisition, multiprocessor interfaces, and commu-

nications buffering.

• 8K x 18 (CY7C4255)

• 16K x 18 (CY7C4265)

• 0.5 micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10-ns read/write cycle

times)

• Low power — I_CC= 45 mA

• Fully asynchronous and simultaneous read and write

operation

These FIFOs have 18-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a Free-Running Clock (WCLK) and a Write

Enable pin (WEN). When WEN is asserted, data is written into the

FIFO on the rising edge of the WCLK signal. While WEN is held

active, data is continually written into the FIFO on each cycle. The

output port is controlled in a similar manner by a free-running Read

Clock (RCLK) and a Read Enable pin (REN). In addition, the

CY7C4255/65 have an Output Enable pin (OE). The read and write

clocks may be tied together for single-clock operation or the two

clocks may be run independently for asynchronous read/write appli-

cations. Clock frequencies up to 100 MHz are achievable.

• Empty, Full, HalfFull, andprogrammableAlmostEmpty

and Almost Full status flags

• TTL compatible

• Retransmit function

• Output Enable (OE) pins

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

• Depth Expansion Capability

Depth expansion is possible using the Cascade Input (WXI,

RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The

WXO and RXO pins are connected to the WXI and RXI pins of the

next device, and the WXO and RXO pins of the last device should be

connected to the WXI and RXI pins of the first device. The FL pin of

the first device is tied to V_SSand the FL pin of all the remaining

• 64-pin TQFP and 64-pin STQFP

• Pin-compatible density upgrade to CY7C42X5 family

• Pin-compatible density upgrade to

IDT72205/15/25/35/45

devices should be tied to V_CC

0–17

Logic Block Diagram

INPUT

WCLK

WEN

FLAG

PROGRAM

WRITE

CONTROL

FLAG

LOGIC

RAM

PAE

PAF

ARRAY

8K x 18

16K x 18

SMODE

WRITE

READ

POINTER

RESET

LOGIC

FL/RT

THREE–STATE

OUTPUTREGISTER

READ

CONTROL

WXI

WXO/HF

RXI

EXPANSION

LOGIC

RXO

0–17

RCLK

REN

Cypress Semiconductor Corporation

Document #: 38-06004 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 2, 2005

12 3 4 5 6 7...22

中文翻译

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与CY7C4255_05相关器件

型号	品牌	获取价格	描述	数据表
CY7C4255_09	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4255-10	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4255-10AC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4255-10ACT	CYPRESS	获取价格	FIFO, 8KX18, 8ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64
CY7C4255-10ASC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4255-10AXC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4255-10AXCT	CYPRESS	获取价格	FIFO, 8KX18, 8ns, Synchronous, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTI
CY7C4255-10JCT	CYPRESS	获取价格	FIFO, 8KX18, 8ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68
CY7C4255-15	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs
CY7C4255-15AC	CYPRESS	获取价格	8K/16K x 18 Deep Sync FIFOs

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