CY7C4022KV13/CY7C4042KV13
■ For a × 18 data width part, 21 address pins plus 1 parity bit are
used for 22 signals in the address group. If the number of 0’s
in the address group is > 12, AINV is set to 1 by the controller.
As a result, no more than 12 pins may switch in the same
direction during each bit time.
Note The memory controller should generate address parity
based on the address bus first. Address inversion is done later
on the address bus and address parity bit.
Port Enable
The QDR-IV XP SRAM has two independent bidirectional data
ports. However, some system designers may either choose to
use only one port, or use one port as read-only and one port as
write-only.
The DINVA and DINVB pins indicate whether the corresponding
DQA and DQB pins are inverted.
■ For a × 36 data width part, the data bus for each port is split
into groups of 18 pins. Each 18-pin data group is guaranteed
to be driving less than or equal to 10 pins low on any given
cycle. If the number of 0’s in the data group is >10, DINV is set
to 1.As a result, no more than 10 pins may switch in the same
direction during each bit time.
If a port is used in a uni-directional mode, disable the data clocks
(DKx/DKx# or QKx/QKx#) to reduce EMI effects in the system.
In addition, disable the corresponding control input (RWx#).
Port B may be programmed to be entirely disabled. If port B is
not used, then the following must happen:
■ For a × 18 data width part, the data bus for each port is split
into groups of 9 pins. Each 9 pin data group is guaranteed to
be driving less than or equal to five pins low on any given cycle.
If the number of 0’s in the data group is >5, DINV is set to 1 As
a result, no more than five pins may switch in the same direction
during each bit time.
■ The data clocks (DKB/DKB# and QKB/QKB#) and the control
inputs (LDB# and RWB#) must be disabled.
■ All data bus signals must be tristated. This includes DQB,
DINVB and QVLDB.
■ All input signals related to port B can be left floating or tied to
either 1 or 0 without any adverse effects on the port A operation.
AINV, DINVA[1:0], DINVB[1:0] are all active high. When set to 1,
the corresponding bus is inverted. If the data inversion feature is
programmed to be OFF, then the DINVA/DINVB output bits will
always be driven to 0.
■ When port B is not used. All output signals related to port B are
inactive.
These functions are programmable through the configuration
registers and can be enabled or disabled for the address bus and
the data bus independently.
A configuration register option is provided to specify if one of the
ports is not used or is operating in a unidirectional mode.
On-Die Termination (ODT) Operation
During configuration register read and write cycles, the address
inversion input is ignored and the data inversion output is always
driven to 0 when the register read data is driven on the data bus.
Specifically, the register read data is driven on DQA[7:0] and the
DINVA[0] bit is driven to 0. All other DQA/DQB data bits and
DINVA/DINVB bits are tristated. In addition, the address parity
input (AP) is ignored.
When enabled, the ODT circuits for the chip will be enabled
during all NOP and write cycles. The ODT is temporary disabled
only during read cycles because the read data is driven out.
Specifically, ODT is disabled one-half clock cycle before the first
beat of the read data is driven on the data bus and remains
disabled during the entire read operation. ODT is enabled again
one-half clock cycle after the last beat of read data is driven on
the data bus.
Address Parity
The QDR-IV XP SRAM provides an address parity feature to
provide integrity on the address bus. Two pins are provided to
support this function: AP and PE#.
JTAG Operation
The JTAG interface uses five signals: TRST#, TCK, TMS, TDI,
and TDO. For normal JTAG operation, the use of TRST# is not
optional for this device.
The AP pin is used to provide an even parity across the address
pins. The value of AP is set so that the total number of 1’s
(including the AP bit) is even. The AP pin is a DDR input.
While in the JTAG mode, the following conditions are true:
Internally, when an address parity error is detected, the access
to the memory array is ignored if it was a write cycle. A read
access continues normally even if an address parity error is
detected.
■ ODT for all pins is disabled.
If the JTAG function is not used in the system, then the TRST#
pin must be tied to VDD and the TCK input must be driven low
or tied to VSS. TMS, TDI, and TDO may be left floating.
Externally, the PE# pin is used to indicate that an address parity
error has occurred. This pin is Active Low and is set to 0 within
RL cycles after the address parity error is detected. It remains
asserted until the error is cleared through the configuration
registers.
Power Up and Reset
The QDR-IV XP SRAM has specific power up and reset
requirements to guarantee reliable operation.
The address parity function is optional and can be enabled or
disabled in the configuration registers.
Power-Up Sequence
■ Apply VDD before VDDQ
.
During configuration register read and write cycles, the address
parity input is ignored. Parity is not checked during these cycles.
■ Apply VDDQ before VREF or at the same time as VREF
.
Document Number: 001-79552 Rev. *O
Page 10 of 46
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