CY7C4022KV13/CY7C4042KV13
Pin Definitions
Pin Name
I/Os
Pin Description
CK, CK#
Input Clock Address/Command Input Clock. CK and CK# are differential clock inputs. All control and address
input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples
the control and address inputs for port A, while the falling edge of CK samples the control and address
inputs for port B. CK# is 180 degrees out of phase with CK.
A[x:0]
Input
Address Inputs. Sampled on the rising edge of both CK and CK# clocks during active read and write
operations. These address inputs are used for read and write operations on both ports. The lower
three address pins (A0, A1, and A2) select the bank that will be accessed. These address inputs are
also known as bank address pins.
For (× 36) data width - Address inputs A[19:0] are used and A[24:20] are reserved.
For (× 18) data width - Address inputs A[20:0] are used and A[24:21] are reserved.
The reserved address inputs are No Connects and may be tied high, tied low, or left floating.
AP
Input
Address Parity Input. Used to provide even parity across the address pins.
For (× 36) data width - AP covers address inputs A[20:0]
For (× 18) data width - AP covers address inputs A[21:0]
PE#
Output
Input
Address Parity Error Flag. Asserted LOW when address parity error is detected. Once asserted,
PE# will remain LOW until cleared by a Configuration Register command.
AINV
Address Inversion Pin for Address and Address Parity Inputs.
For (× 36) data width - AINV covers address inputs A[20:0] and the address parity input (AP).
For (× 18) data width - AINV covers address inputs A[21:0] and the address parity input (AP).
DKA[1:0],
DKA#[1:0],
DKB[1:0],
DKB#[1:0]
Input
Data Input Clock.
DKA[0]/DKA#[0] controls the DQA[17:0] inputs for × 36 configuration and DQA[8:0] inputs for × 18
configuration respectively
DKA[1]/DKA#[1] controls the DQA[35:18] inputs for × 36 configuration and DQA[17:9] inputs for × 18
configuration respectively
DKB[0]/DKB#[0] controls the DQB[17:0] inputs for × 36 configuration and DQB[8:0] inputs for × 18
configuration respectively
DKB[1]/DKB#[1] controls the DQB[35:18] inputs for × 36 configuration and DQB[17:9] inputs for × 18
configuration respectively
QKA[1:0],
QKA#[1:0],
QKB[1:0],
QKB#[1:0]
Output
Data Output Clock.
QKA[0]/QKA#[0] controls the DQA[17:0] outputs for ×36 configuration and DQA[8:0] outputs for × 18
configuration respectively
QKA[1]/QKA#[1] controls the DQA[35:18] outputs for × 36 configuration and DQA[17:9] outputs for
× 18 configuration respectively
QKB[0]/QKB#[0] controls the DQB[17:0] outputs for × 36 configuration and DQB[8:0] outputs for × 18
configuration respectively
QKB[1]/QKB#[1] controls the DQB[35:18] outputs for × 36 configuration and DQB[17:9] outputs for
× 18 configuration respectively
Input/Output Data Input/Output.Bidirectional data bus.
For (× 36) data width DQA[35:0]; DQB[35:0]
DQA[x:0],
DQB[x:0]
For (× 18) data width DQA[17:0]; DQB[17:0]
Input/Output Data Inversion Pin for DQ Data Bus.
DINVA[1:0],
DINVB[1:0]
DINVA[0] covers DQA[17:0] for × 36 configuration and DQA[8:0] for × 18 configuration respectively
DINVA[1] covers DQA[35:18] for × 36 configuration and DQA[17:9] for × 18 configuration respectively
DINVB[0] covers DQB[17:0] for × 36 configuration and DQB[8:0] for × 18 configuration respectively
DINVB[1] covers DQB[35:18] for × 36 configuration and DQB[17:9] for × 18 configuration respectively
LDA#, LDB#
Input
Synchronous Load Input.LDA# is sampled on the rising edge of the CK clock, while LDB# is sampled
on the falling edge of CK clock. LDA# enables commands for data port A, and LDB# enables
commands for data port B. LDx# enables the commands when LDx# is LOW and disables the
commands when LDx# is HIGH. When the command is disabled, new commands are ignored, but
internal operations continue.
Document Number: 001-79552 Rev. *O
Page 7 of 46
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