1CY7C409A
CY7C408A
CY7C409A
64 x 8 Cascadable FIFO
64 x 9 Cascadable FIFO
same order as it was stored on the DO – DO output pins
Features
0
8
under the control of the shift out (SO) input when the output
ready (OR) control signal is HIGH. If the FIFO is full (IR LOW),
pulses at the SI input are ignored; if the FIFO is empty (OR
LOW), pulses at the SO input are ignored.
• 64 x 8 and 64 x 9 first-in first-out (FIFO) buffer memory
• 35-MHz shift in and shift out rates
• Almost Full/Almost Empty and Half Full flags
• Dual-port RAM architecture
• Fast (50-ns) bubble-through
• Independent asynchronous inputs and outputs
• Output enable (CY7C408A)
• Expandable in word width and FIFO depth
• 5V ± 10% supply
• TTL complete
• Capable of withstanding greater than 2001V electro-
static discharge voltage
• 300-mil, 28-pin DIP
The IR and OR signals are also used to connect the FIFOs in
parallel to make a wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is implemented by logically
ANDing the IR an OR outputs (respectively) of the individual
FIFOs together (Figure 5). The AND operation insures that all
of the FIFOs are either ready to accept more data (IR HIGH)
or ready to output data (OR HIGH) and thus compensate for
variations in propagation delay times between devices.
Serial expansion (cascading) for deeper buffer memories is
accomplished by connecting data outputs of the FIFO closet
to the data source (upstream device) to the data inputs of the
following (downstream) FIFO (Figure 4). In addition, to insure
proper operation, the SO signal of the upstream FIFO must be
connected to the OR output of the upstream FIFO. In this serial
expansion configuration, the IR and OR signals are used to
pass data through the FIFOs.
Functional Description
The CY7C408A and CY7C409A are 64-word deep by 8- or
9-bit wide first-in first-out (FIFO) buffer memories. In addition
to the industry-standard handshaking signals, almost full/al-
most empty (AFE) and half-full (HF) flags are provided.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The high
shift in and shift out rates of these FIFOs, and their throughput
rate due to the fast bubblethrough time, which is due to their
dual-port RAM architecture, make them ideal for high-speed
communications and controllers.
AFE is HIGH when the FIFO is almost full or almost empty,
otherwise AFE is LOW. HF is HIGH when the FIFO is half full,
otherwise HF is LOW.
The CY7C408A has an output enable (OE) function.
The memory accepts 8- or 9-bit parallel words as its inputs (DI
0
– DI ) under the control of the shift in (SI) input when the input
8
ready (IR) control signal is HIGH. The data is output, in the
Pin Configurations
Logic Block Diagram
AFE
1
2
3
4
5
6
7
8
9
28
27
26
25
V
CC
ALMOSTFULL/
WRITE POINTER
AFE
HF
SI
IR
HF
IR
SI
MR
SO
OR
INPUT
CONTROL
LOGIC
ALMOSTEMPTY
WRITEMULTIPLEXER
HALF FULL
DI
0
24 DO
0
DO
.
0
7
DI
1
23
22
21 DO
DO
1
.
.
7C408A
7C409A
DI
GND
0
.
GND
MEMORY
ARRAY
DO
.
.
DI
DI
2
2
3
DATA IN
DATAOUT
20 DO
3
DI
7
8
DO (7C409A)
8
10
11
12
13
14
DO
19
18
17
16
15
DI
DI
DI
4
4
5
6
(7C409A)
DI
DO
5
DO
6
DO
7
OE (7C408A)
DO (7C409A)
8
OE (7C408A)
READ MULTIPLEXER
READPOINTER
DI
7
OUTPUT
CONTROL
LOGIC
MASTER
RESET
OR
SO
(7C408A) NC
(7C409A) DI
8
MR
C408A–3
C408A–1
4 3
2
28 2726
1
Flag Definitions
DI
DI
GND
DI
2
DI
DI
DI
OR
DO
DO
GND
DO
0
1
25
24
23
22
21
20
19
5
6
7
8
9
10
11
0
1
HF
L
AFE
H
Words Stored
0 - 8
7C408A
7C409A
3
4
5
2
DO
3
L
L
9 - 31
DO
4
121314 151617 18
H
H
L
32 - 55
H
56 - 64
C408A–2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
July 1986 – Revised July 1994
•
408-943-2600