Datasheet > CY7C4042KV13-933FCXC

CY7C4042KV13-933FCXC

更新时间： 2024-03-03 10:10:20

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
46页	1159K
描述
Synchronous SRAM

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中文翻译

获取价格

数据手册

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CY7C4042KV13-933FCXC 数据手册

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CY7C4022KV13/CY7C4042KV13

Pin Definitions (continued)

Pin Name

I/Os

Pin Description

RWA#,

RWB#

Input

Synchronous Read/Write Input. RWA# input is sampled on the rising edge of the CK clock, while

RWB# is sampled on the falling edge of the CK clock. The RWA# input is used in conjunction with the

LDA# input to select a Read or Write Operation. Similarly, the RWB# input is used in conjunction with

the LDB# input to select a read or write operation.

QVLDA

QVLDB

Output

Input

Output Data Valid Indicator. The QVLD pin indicates valid output data. QVLD is edge aligned with

QKx and QKx#.

[1:0],

[1:0]

ZQ/ZT

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

bus impedance.

CFG#

RST#

Input

Configuration bit. This pin is used to configure different mode registers.

Active Low Asynchronous RST. This pin is active when RST# is LOW and inactive when RST# is

HIGH. The RST# pin has an internal pull down resistor.

LBK0#,

LBK1#

Input

Output

Input

Loopback mode for control and address/command/clock deskewing.

TMS

Test Mode Select Input pin for JTAG. This pin may be left unconnected if the JTAG function is not

used in the circuit.

TDI

Test Data Input pin for JTAG. This pin may be left unconnected if the JTAG function is not used in

the circuit.

TCK

Test Clock Input pin for JTAG. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

TDO

TRST#

Test Data Output pin for JTAG. This pin may be left unconnected if the JTAG function is not used in

the circuit.

Test Reset Input pin for JTAG. This pin must be tied to VDD if the JTAG function is not used in the

system. TRST# input is applicable only in JTAG mode.

DNU

N/A

Do Not Use. Do Not Use pins.

VREF

Reference

Reference Voltage Input. Static input used to set the reference level for inputs, outputs, and AC

measurement points.

VDD

Power

Ground

Power Supply Inputs to the Core of the Device.

Power Supply Inputs for the Outputs of the Device.

Ground for the Device.

VDDQ

VSS

Document Number: 001-79552 Rev. *O

Page 8 of 46

1...5 6 789 10 11...46

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与CY7C4042KV13-933FCXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C408A-15DC	CYPRESS	获取价格	FIFO, 64X8, 40ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERDIP-28
CY7C408A-15DMB	CYPRESS	获取价格	64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO
CY7C408A-15KMB	CYPRESS	获取价格	FIFO, 64X8, 40ns, Asynchronous, CMOS, CDFP28, GLASS SEALED, CERPACK-28
CY7C408A-15LC	ETC	获取价格	x8 Asynchronous FIFO
CY7C408A-15LMB	CYPRESS	获取价格	64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO
CY7C408A-15LMBR	CYPRESS	获取价格	FIFO, 64X8, 40ns, Asynchronous, CMOS, CQCC28, CERAMIC, LCC-28
CY7C408A-15LMBT	CYPRESS	获取价格	FIFO, 64X8, 40ns, Asynchronous, CMOS, CQCC28, CERAMIC, LCC-28
CY7C408A-15PC	CYPRESS	获取价格	64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO
CY7C408A-15VC	CYPRESS	获取价格	64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO
CY7C408A-15VCT	CYPRESS	获取价格	FIFO, 64X8, 40ns, Asynchronous, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

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