Datasheet > CY7C4042KV13-106FCXC

CY7C4042KV13-106FCXC

更新时间： 2024-02-12 18:47:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
46页	1165K
描述
72-Mbit QDRâ¢-IV XP SRAM

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CY7C4042KV13-106FCXC 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	HBGA,	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.78	JESD-30 代码：	S-PBGA-B361
长度：	21 mm	内存密度：	75497472 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
功能数量：	1	端子数量：	361
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	HBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, HEAT SINK/SLUG
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	2.765 mm	最大供电电压 (Vsup)：	1.34 V
最小供电电压 (Vsup)：	1.26 V	标称供电电压 (Vsup)：	1.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	21 mm
Base Number Matches：	1

CY7C4042KV13-106FCXC 数据手册

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CY7C4022KV13/CY7C4042KV13

Pin Definitions

Pin Name

I/Os

Pin Description

CK, CK#

Input Clock Address/Command Input Clock. CK and CK# are differential clock inputs. All control and address

input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples

the control and address inputs for port A, while the falling edge of CK samples the control and address

inputs for port B. CK# is 180 degrees out of phase with CK.

A[x:0]

Input

Address Inputs. Sampled on the rising edge of both CK and CK# clocks during active read and write

operations. These address inputs are used for read and write operations on both ports. The lower

three address pins (A0, A1, and A2) select the bank that will be accessed. These address inputs are

also known as bank address pins.

For (× 36) data width - Address inputs A[19:0] are used and A[24:20] are reserved.

For (× 18) data width - Address inputs A[20:0] are used and A[24:21] are reserved.

The reserved address inputs are No Connects and may be tied high, tied low, or left floating.

Input

Address Parity Input. Used to provide even parity across the address pins.

For (× 36) data width - AP covers address inputs A[20:0]

For (× 18) data width - AP covers address inputs A[21:0]

PE#

Output

Input

Address Parity Error Flag. Asserted LOW when address parity error is detected. Once asserted,

PE# will remain LOW until cleared by a Configuration Register command.

AINV

Address Inversion Pin for Address and Address Parity Inputs.

For (× 36) data width - AINV covers address inputs A[20:0] and the address parity input (AP).

For (× 18) data width - AINV covers address inputs A[21:0] and the address parity input (AP).

DKA[1:0],

DKA#[1:0],

DKB[1:0],

DKB#[1:0]

Input

Data Input Clock.

DKA[0]/DKA#[0] controls the DQA[17:0] inputs for × 36 configuration and DQA[8:0] inputs for × 18

configuration respectively

DKA[1]/DKA#[1] controls the DQA[35:18] inputs for × 36 configuration and DQA[17:9] inputs for × 18

configuration respectively

DKB[0]/DKB#[0] controls the DQB[17:0] inputs for × 36 configuration and DQB[8:0] inputs for × 18

configuration respectively

DKB[1]/DKB#[1] controls the DQB[35:18] inputs for × 36 configuration and DQB[17:9] inputs for × 18

configuration respectively

QKA[1:0],

QKA#[1:0],

QKB[1:0],

QKB#[1:0]

Output

Data Output Clock.

QKA[0]/QKA#[0] controls the DQA[17:0] outputs for ×36 configuration and DQA[8:0] outputs for × 18

configuration respectively

QKA[1]/QKA#[1] controls the DQA[35:18] outputs for × 36 configuration and DQA[17:9] outputs for

× 18 configuration respectively

QKB[0]/QKB#[0] controls the DQB[17:0] outputs for × 36 configuration and DQB[8:0] outputs for × 18

configuration respectively

QKB[1]/QKB#[1] controls the DQB[35:18] outputs for × 36 configuration and DQB[17:9] outputs for

× 18 configuration respectively

Input/Output Data Input/Output.Bidirectional data bus.

For (× 36) data width  DQA_[35:0]; DQB_[35:0]

DQA[x:0],

DQB[x:0]

For (× 18) data width  DQA_[17:0]; DQB_[17:0]

Input/Output Data Inversion Pin for DQ Data Bus.

DINVA[1:0],

DINVB[1:0]

DINVA[0] covers DQA[17:0] for × 36 configuration and DQA[8:0] for × 18 configuration respectively

DINVA[1] covers DQA[35:18] for × 36 configuration and DQA[17:9] for × 18 configuration respectively

DINVB[0] covers DQB[17:0] for × 36 configuration and DQB[8:0] for × 18 configuration respectively

DINVB[1] covers DQB[35:18] for × 36 configuration and DQB[17:9] for × 18 configuration respectively

LDA#, LDB#

Input

Synchronous Load Input.LDA# is sampled on the rising edge of the CK clock, while LDB# is sampled

on the falling edge of CK clock. LDA# enables commands for data port A, and LDB# enables

commands for data port B. LDx# enables the commands when LDx# is LOW and disables the

commands when LDx# is HIGH. When the command is disabled, new commands are ignored, but

internal operations continue.

Document Number: 001-79552 Rev. *O

Page 7 of 46

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CY7C408A-15DC	CYPRESS	FIFO, 64X8, 40ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERDIP-28	获取价格
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