Datasheet > CY7C4042KV13-933FCXC

CY7C4042KV13-933FCXC

更新时间： 2024-01-28 23:40:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
46页	1165K
描述
72-Mbit QDRâ¢-IV XP SRAM

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CY7C4042KV13-933FCXC 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	HBGA,	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	2.34	JESD-30 代码：	S-PBGA-B361
长度：	21 mm	内存密度：	75497472 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
功能数量：	1	端子数量：	361
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	HBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, HEAT SINK/SLUG
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	2.765 mm	最大供电电压 (Vsup)：	1.34 V
最小供电电压 (Vsup)：	1.26 V	标称供电电压 (Vsup)：	1.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	21 mm

CY7C4042KV13-933FCXC 数据手册

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CY7C4022KV13/CY7C4042KV13

72-Mbit QDR™-IV XP SRAM

Features

Configurations

■ 72-Mbit density (4M × 18, 2M × 36)

■ Total Random Transaction Rate^[1]of 2132 MT/s

CY7C4022KV13 – 4M × 18

CY7C4042KV13 – 2M × 36

■ Maximum operating frequency of 1066 MHz

Functional Description

■ Read latency of 8.0 clock cycles and Write Latency of 5.0 clock

The QDR™-IV XP (Xtreme Performance) SRAM is

high-performance memory device that has been optimized to

maximize the number of random transactions per second by the

use of two independent bi-directional data ports.

cycles

■ 8 bank architecture enables one access per bank per cycle

■ Two-word burst on all accesses

These ports are equipped with DDR interfaces and designated

as port A and port B respectively. Accesses to these two data

ports are concurrent and independent of each other. Access to

each port is through a common address bus running at DDR. The

control signals are running at SDR and determine if a read or

write should be performed.

■ Dual independent bi-directional data ports

❐ Double data rate (DDR) data ports

❐ Supports concurrent read/write transactions on both ports

■ Single address port used to control both data ports

❐ DDR address signaling

There are three types of differential clocks:

■ Single data rate (SDR) control signaling

■ (CK, CK#) for address and command clocking

■ (DKA, DKA#, DKB, DKB#) for data input clocking

■ (QKA, QKA#, QKB, QKB#) for data output clocking

■ High-speed transceiver logic (HSTL) and stub series

terminated logic (SSTL) compatible signaling (JESD8-16A

compliant)

❐ I/O V_DDQ= 1.2 V ± 50 mV or 1.25 V ± 50 mV

Addresses for port A are latched on the rising edge of the input

clock (CK), and addresses for port B are latched on the falling

edge of the input clock (CK).

■ Pseudo open drain (POD) signaling (JESD8-24 compliant)

❐ I/O V_DDQ= 1.1 V ± 50 mV or 1.2 V ± 50 mV

■ Core voltage

❐ V_DD= 1.3 V ± 40 mV

This QDR-IV XP SRAM is internally partitioned into eight internal

banks. Each bank can be accessed once for every clock cycle

enabling the SRAM to operate at high frequencies.

■ On-die termination (ODT)

❐ Programmable for clock, address/command and data inputs

The QDR-IV XP SRAM device is offered in a two-word burst

option and is available in × 18 and × 36 bus width configurations.

■ Internal self calibration of output impedance through ZQ pin

For an × 18 bus width configuration, there are 22 address bits,

and for an × 36 bus width configuration, there are 21 address bits

respectively.

■ Bus inversion to reduce switching noise and power

❐ Programmable on/off for address and data

An on-chip ECC circuitry detects and corrects all single-bit

memory errors, including those induced by soft error events such

as cosmic rays, alpha particles, etc. The resulting SER of these

devices is expected to be less than 0.01 FITs/Mb, a

four-order-of-magnitude improvement over previous generation

SRAMs.

■ Address bus parity error protection

■ Training sequence for per-bit deskew

■ On-chip error correction code (ECC) to reduce soft error rate

(SER)

■ JTAG 1149.1 test access port (JESD8-26 compliant)

❐ 1.3-V LVCMOS signaling

For a complete list of related resources, click here.

■ Available in 361-ball FCBGA Pb-free package (21 × 21 mm)

Selection Guide

QDR-IV

2132 (MT/s)

QDR-IV

1866 (MT/s)

Description

Unit

Maximum Operating Frequency

Maximum Operating Current

1066

4100

4500

933

3400

4000

MHz

× 18

× 36

Note

1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured

in million transactions per second.

Cypress Semiconductor Corporation

Document Number: 001-79552 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 3, 2017

12 3 4 5 6 7...46

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