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CY7C404-25LMBR PDF预览

CY7C404-25LMBR

更新时间： 2024-01-15 15:49:26
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
13页 273K
描述
FIFO, 64X5, 37ns, Asynchronous, CMOS, CQCC20, LCC-20

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CY7C404-25LMBR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：0.300 INCH, DIP-18
针数：18Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.79最长访问时间：34 ns
其他特性：BUBBLE BACK 50NS最大时钟频率 (fCLK)：25 MHz
周期时间：40 nsJESD-30 代码：R-PDIP-T18
JESD-609代码：e0长度：22.733 mm
内存密度：320 bit内存集成电路类型：OTHER FIFO
内存宽度：5功能数量：1
端子数量：18字数：64 words
字数代码：64工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64X5输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP18,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：4.826 mm子类别：FIFOs
最大压摆率：0.075 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

CY7C404-25LMBR 数据手册

 浏览型号CY7C404-25LMBR的Datasheet PDF文件第5页浏览型号CY7C404-25LMBR的Datasheet PDF文件第6页浏览型号CY7C404-25LMBR的Datasheet PDF文件第7页浏览型号CY7C404-25LMBR的Datasheet PDF文件第9页浏览型号CY7C404-25LMBR的Datasheet PDF文件第10页浏览型号CY7C404-25LMBR的Datasheet PDF文件第11页 
CY7C401/CY7C403  
CY7C402/CY7C404  
FIFO Expansion[13, 14, 15, 16, 17]  
[18]  
128 x 4 Application  
SHIFT IN  
SI  
IR  
OR  
SO  
SI  
IR  
OR  
SO  
OUTPUT READY  
SHIFT OUT  
INPUT READY  
DI  
0
DO  
DI  
0
DO  
0
0
DI  
DO  
DI  
DO  
1
1
1
1
DATA OUT  
DATA IN  
DO  
DO  
2
DI  
2
DI  
2
2
DI  
3
MR DO  
DI  
3
MR DO  
3
3
MR  
C401–16  
[19]  
192 x 12 Application  
SHIFT OUT  
IR  
SI  
SO  
OR  
IR  
SI  
SO  
OR  
IR  
SI  
DI  
SO  
OR  
DO  
DI  
0
DO  
DI  
0
DO  
0
0
0
0
DI  
1
DO  
DI  
1
DO  
DI  
1
DO  
1
1
1
DO  
DO  
DO  
2
DI  
2
DI  
2
DI  
2
2
2
DI MR DO  
DI MR DO  
DI MR DO  
3 3  
3
3
3
3
COMPOSITE  
INPUT READY  
COMPOSITE  
OUTPUT READY  
IR  
SI  
DI  
SO  
OR  
IR  
SI  
DI  
SO  
OR  
IR  
SI  
DI  
SO  
OR  
DO  
DO  
DO  
0
0
0
0
0
0
DI  
1
DO  
DI  
1
DO  
DI  
1
DO  
1
1
1
DO  
DO  
DO  
2
DI  
2
DI  
2
DI  
2
2
2
DI MR DO  
DI MR DO  
DI MR DO  
3 3  
3
3
3
3
SHIFT IN  
IR  
SI  
DI  
SO  
OR  
IR  
SI  
DI  
SO  
OR  
IR  
SI  
DI  
SO  
OR  
DO  
DO  
DO  
0
0
0
0
0
0
DI  
1
DO  
DI  
1
DO  
DI  
1
DO  
1
1
1
DO  
DO  
DO  
2
DI  
2
DI  
2
DI  
2
2
2
DI MR DO  
DI MR DO  
DI MR DO  
3 3  
3
3
3
3
MR  
C401–17  
Notes:  
13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output.  
However, OR will remain LOW, indicating data at the output is not valid.  
14. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data, and stays LOW  
until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs.  
15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH  
for one internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO,  
they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.  
16. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH,  
then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset  
is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.  
17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pin-compatible FIFOs from other manufacturers.  
18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the  
devices.  
19. FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready  
flags. This need is due to the variation of delays of the FIFOs.  
8
1...567891011...13

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