Datasheet > CY7C346(B)

CY7C346(B)

更新时间： 2024-10-05 12:49:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
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6页	87K
描述
Multiple Array Matrix High-Density EPLDs

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CY7C346(B) 数据手册

EPLD

CY7C340 EPLD Family

Multiple Array Matrix High-Density EPLDs

CY7C342B. This allows the designer to replace 50 or more

TTL packages with just one MAX EPLD. The family comes in

a range of densities, shown below. By standardizing on a few

MAX building blocks, the designer can replace hundreds of

different 7400 series part numbers currently used in most dig-

ital systems.

Features

• Erasable, user-configurable CMOS EPLDs capable of

implementing high-density custom logic functions

• 0.8-micron double-metal CMOS EPROM technology

(CY7C34X)

The family is based on an architecture of flexible macrocells

grouped together into Logic Array Blocks (LABs). Within the

LAB is a group of additional product terms called expander

product terms. These expanders are used and shared by the

macrocells, allowing complex functions of up to 35 product

terms to be easily implemented in a single macrocell. A Pro-

grammable Interconnect Array (PIA) globally routes all signals

within devices containing more than one LAB. This architec-

ture is fabricated on the Cypress 0.8-micron, double-lay-

er-metal CMOS EPROM process, yielding devices with signif-

icantly higher integration, density and system clock speed than

the largest of previous generation EPLDs. The CY7C34XB de-

vices are 0.65-micron shrinks of the original 0.8-micron family.

The CY7C34XBs offer faster speed bins for each device in the

Cypress MAX family.

• Advanced 0.65-micron CMOS technology to increase

performance (CY7C34XB)

• Multiple Array MatriX architecture optimized for speed,

density, and straightforward design implementation

— Programmable Interconnect Array (PIA) simplifies

routing

— Flexible macrocells increase utilization

— Programmable clock control

— Expander product terms implement complex logic

functions

General Description

The Cypress Multiple Array Matrix (MAX®) family of EPLDs

provides a user-configurable, high-density solution to gener-

al-purpose logic integration requirements. With the combina-

tion of innovative architecture and state-of-the-art process, the

MAX EPLDs offer LSI density without sacrificing speed.

The density and performance of the CY7C340 family is ac-

cessed using Cypress’s Warp™, Warp Professional™, or

Warp Enterprise™ design software. Warp provides

state-of-the-art synthesis, fitting, simulation and other devel-

opment tools at a very low cost. Warp Professional or Warp

Enterprise are sophisticated CAE tool that include behavior-

al simulation, graphical waveform editing and more. Consult

the datasheets for Warp, Warp Professional and Warp Enter-

prise™ for more information about these development tools.

The MAX architecture makes it ideal for replacing large

amounts of TTL SSI and MSI logic. For example, a 74161

counter utilizes only 3% of the 128 macrocells available in the

CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes

less than 1% of the over 1,000 product terms in the

Max Family Members

Feature

Macrocells

CY7C344(B)

CY7C343(B)

CY7C342B

128

CY7C346(B)

CY7C341B

192

128

MAX Flip-Flops

128

192

[1]

MAX Latches

128

256

384

[2]

MAX Inputs

MAX Outputs

Packages

28H,J,W,P

44H,J

68H,J,R

84H,J 100R,N

84H,J,R

Key: P—Plastic DIP; H—Windowed Ceramic Leaded Chip Carrier; J—Plastic J-Lead Chip Carrier; R—Windowed Pin Grid Array;

W—Windowed Ceramic DIP; N—Plastic Quad Flat Pack

Notes:

1. When all expander product terms are used to implement latches.

2. With one output.

PAL is a registered trademark of Advanced Micro Devices.

MAX is a registered trademark of Altera Corporation.

FLASH370, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

July 19, 2000

12 3 4 5 6

中文翻译

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与CY7C346(B)相关器件

型号	品牌	获取价格	描述	数据表
CY7C346-25	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25HC	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25HI	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25JC	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25JCR	CYPRESS	获取价格	OT PLD, 52ns, CMOS, PQCC84, PLASTIC, LCC-84
CY7C346-25JI	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25NC	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25NI	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25RC	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)
CY7C346-25RI	CYPRESS	获取价格	USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)

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