生命周期: | Obsolete | 零件包装代码: | LCC |
包装说明: | QCCJ, | 针数: | 84 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.82 | 其他特性: | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
最大时钟频率: | 33.3 MHz | JESD-30 代码: | S-PQCC-J84 |
长度: | 29.3116 mm | 专用输入次数: | 19 |
I/O 线路数量: | 48 | 端子数量: | 84 |
最高工作温度: | 70 °C | 最低工作温度: | |
组织: | 19 DEDICATED INPUTS, 48 I/O | 输出函数: | MACROCELL |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | QCCJ |
封装形状: | SQUARE | 封装形式: | CHIP CARRIER |
可编程逻辑类型: | OT PLD | 传播延迟: | 52 ns |
认证状态: | Not Qualified | 座面最大高度: | 5.08 mm |
最大供电电压: | 5.25 V | 最小供电电压: | 4.75 V |
标称供电电压: | 5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | COMMERCIAL |
端子形式: | J BEND | 端子节距: | 1.27 mm |
端子位置: | QUAD | 宽度: | 29.3116 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CY7C346-25JI | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-25NC | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-25NI | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-25RC | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-25RI | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-30 | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-30HC | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-30HI | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-30HMB | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) | |
CY7C346-30JC | CYPRESS |
获取价格 |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) |