Datasheet > CY7C2670KV18-550BZI

CY7C2670KV18-550BZI

更新时间： 2024-11-08 14:53:51

品牌	Logo	应用领域
英飞凌 - INFINEON		双倍数据速率
页数	文件大小	规格书
29页	741K
描述
DDR-II+ CIO

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CY7C2670KV18

144-Mbit DDR II+ SRAM Two-Word Burst

Architecture (2.5 Cycle Read Latency) with ODT

144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

Configurations

■ 144-Mbit density (4 M × 36)

With Read Cycle Latency of 2.5 cycles:

CY7C2670KV18 – 4 M × 36

■ 550-MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) interfaces (data transferred at

1100 MHz) at 550 MHz

The CY7C2670KV18 is 1.8-V synchronous pipelined SRAM

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 36-bit

words (CY7C2670KV18) that burst sequentially into or out of the

device.

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

These devices have an ODT feature supported for D_[x:0]

BWS_[x:0], and K/K inputs, which helps eliminate external

termination resistors, reduce cost, reduce board area, and

simplify board routing.

■ On-die termination (ODT) feature

❐ Supported for D_[x:0], BWS_[x:0], and K/K inputs

■ Synchronous internally self-timed writes

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ DDR II+ operates with 2.5-cycle read latency when DOFF is

asserted high

■ Operatessimilarto DDR Idevice with 1 cycle read latencywhen

DOFF is asserted low

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ High-speed transceiver logic (HSTL) inputs and variable drive

HSTL output buffers

For a complete list of related documentation, click here.

■ Available in 165-ball fine-pitch ball grid array (FBGA) package

(15 × 17 × 1.4 mm)

■ Offered in non Pb-free package.

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

550 MHz

550

450 MHz Unit

450

980

MHz

Maximum operating current

× 36

1140

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-44143 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 4, 2018

12 3 4 5 6 7...29

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与CY7C2670KV18-550BZI相关器件

型号	品牌	获取价格	描述	数据表
CY7C2670KV18-550BZXI	INFINEON	获取价格	DDR-II+ CIO
CY7C268-40DC	ETC	获取价格	x8 EPROM
CY7C268-40WC	ETC	获取价格	x8 EPROM
CY7C268-40WI	CYPRESS	获取价格	UVPROM, 8KX8, 20ns, CMOS, CDIP32, 0.600 INCH, WINDOWED, CERDIP-32
CY7C268-50DC	ETC	获取价格	x8 EPROM
CY7C268-50DI	CYPRESS	获取价格	OTP ROM, 8KX8, 25ns, CMOS, CDIP32, 0.600 INCH, HERMETIC SEALED, CERDIP-32
CY7C268-50DMB	ETC	获取价格	x8 EPROM
CY7C268-50LMB	ETC	获取价格	x8 EPROM
CY7C268-50QMB	ETC	获取价格	x8 EPROM
CY7C268-50WC	CYPRESS	获取价格	UVPROM, 8KX8, 75ns, CMOS, CDIP32, 0.600 INCH, WINDOWED, CERDIP-32

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