CY7C2262XV18, CY7C2264XV18
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
Echo Clocks
Echo clocks are provided on the QDR II+ Xtreme to simplify data
capture on high-speed systems. Two echo clocks are generated
by the QDR II+ Xtreme. CQ is referenced with respect to K and
CQ is referenced with respect to K. These are free running clocks
and are synchronized to the input clock of the QDR II+ Xtreme.
The timing for echo clocks is shown in the Switching
Characteristics on page 23.
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ Xtreme to simplify data capture
on high speed systems. The QVLD is generated by the QDR II+
Xtreme device along with data output. This signal is also
edge-aligned with the echo clock and follows the timing of any
data pin. This signal is asserted half a cycle before valid data
arrives.
Byte Write Operations
Byte write operations are supported by the CY7C2262XV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
On-Die Termination (ODT)
These devices have an On-Die Termination feature for Data
inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K
and K). The termination resistors are integrated within the chip.
The ODT range selection is enabled through ball R6 (ODT pin).
The ODT termination tracks value of RQ where RQ is the resistor
tied to the ZQ pin. ODT range selection is made during power up
initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied
to ZQ pin)A HIGH on this pin selects a high range that follows
RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied
to ZQ pin). When left floating, a high range termination value is
selected by default. For a detailed description on the ODT
implementation, refer to the application note, On-Die Termination
for QDRII+/DDRII+ SRAMs.
Concurrent Transactions
The read and write ports on the CY7C2262XV18 operate
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. The user can start reads and writes in the same clock cycle.
If the ports access the same location at the same time, the SRAM
delivers the most recent information associated with the
specified address location. This includes forwarding data from a
write cycle that was initiated on the previous K clock rise.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
100 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 100 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Depth Expansion
The CY7C2262XV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
Document Number : 001-70330 Rev. *B
Page 7 of 29
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