Datasheet > CY7C2270XV18

CY7C2270XV18

更新时间： 2024-11-20 12:50:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
29页	907K
描述
36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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CY7C2270XV18 数据手册

CY7C2268XV18, CY7C2270XV18

36-Mbit DDR II+ Xtreme SRAM Two-Word

Burst Architecture (2.5 Cycle Read Latency) with ODT

36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

Configurations

■ 36-Mbit density (2 M × 18, 1 M × 36)

With Read Cycle Latency of 2.5 cycles:

CY7C2268XV18 – 2 M × 18

■ 633 MHz clock for high bandwidth

CY7C2270XV18 – 1 M × 36

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at

1266 MHz) at 633 MHz

Functional Description

The CY7C2268XV18, and CY7C2270XV18 are 1.8 V

Synchronous Pipelined SRAMs equipped with DDR II+

architecture. The DDR II+ consists of an SRAM core with

advanced synchronous peripheral circuitry. Addresses for read

and write are latched on alternate rising edges of the input (K)

clock. Write data is registered on the rising edges of both K and

K. Read data is driven on the rising edges of K and K. Each

address location is associated with two 18-bit words

(CY7C2268XV18), or 36-bit words (CY7C2270XV18) that burst

sequentially into or out of the device.

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo Clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

❐ Supported for DQ_[x:0], BWS_[x:0], and K/K inputs

These devices have an On-Die Termination feature supported

for DQ_[x:0], BWS_[x:0], and K/K inputs, which helps eliminate

external termination resistors, reduce cost, reduce board area,

and simplify board routing.

■ Synchronous internally self-timed writes

■ DDR II+ Xtreme operates with 2.5 cycle read latency when

DOFF is asserted HIGH

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ Operates similar to DDR I Device with 1 cycle read latency

when DOFF is asserted LOW

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to 1.6 V

❐ Supports 1.5 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum Operating Frequency

633 MHz

633

600 MHz Unit

600

910

MHz

Maximum Operating Current

× 18

× 36

965

1230

1165

Cypress Semiconductor Corporation

Document Number: 001-70332 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 25, 2012

12 3 4 5 6 7...29

中文翻译

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与CY7C2270XV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C2270XV18-633BZXC	INFINEON	获取价格	DDR-II+ CIO
CY7C235-25DC	ETC	获取价格	x8 EPROM
CY7C235-25JC	ETC	获取价格	x8 EPROM
CY7C235-25JCR	CYPRESS	获取价格	OTP ROM, 1KX8, CMOS, PQCC28, PLASTIC, LCC-28
CY7C235-25JCT	CYPRESS	获取价格	OTP ROM, 1KX8, CMOS, PQCC28, PLASTIC, LCC-28
CY7C235-25JI	CYPRESS	获取价格	OTP ROM, 1KX8, 12ns, CMOS, PQCC28, PLASTIC, LCC-28
CY7C235-25JIT	CYPRESS	获取价格	OTP ROM, 1KX8, 12ns, CMOS, PQCC28, PLASTIC, LCC-28
CY7C235-25PC	ETC	获取价格	x8 EPROM
CY7C235-30DC	ETC	获取价格	x8 EPROM
CY7C235-30DI	CYPRESS	获取价格	OTP ROM, 1KX8, CMOS, CDIP24, 0.300 INCH, SLIM, HERMETIC SEALED, CERDIP-24

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