CY7C2262XV18, CY7C2264XV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The
timing in the operation with the PLL turned off differs from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 k or less pull up resistor. The device behaves in
QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up
to 167 MHz with QDR I timing.
TDO
Output
Input
Input
Input
N/A
TDO Pin for JTAG.
TCK
TCK Pin for JTAG.
TDI
TDI Pin for JTAG.
TMS
TMS Pin for JTAG.
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
NC/72M
NC/144M
NC/288M
VREF
Input
Input
Input
Input-
Reference measurement points.
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
VDDQ
Power Supply Power Supply Inputs for the Outputs of the Device.
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the input clocks (K and K) as well.
Functional Overview
The CY7C2262XV18, and CY7C2264XV18 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II+ Xtreme completely eliminates the need to “turn
around” the data bus and avoids any possible data contention,
thereby simplifying system design. Each access consists of two
18-bit data transfers in the case of CY7C2262XV18, and two
36-bit data transfers in the case of CY7C2264XV18 in one clock
cycle.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C2262XV18 is described in the following sections. The
same basic descriptions apply to CY7C2264XV18.
Read Operations
The CY7C2262XV18 is organized internally as two arrays of
1 M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next two K clock rise, the corresponding
lowest order 18-bit word of data is driven onto the Q[17:0] using
K as the output timing reference. On the subsequent rising edge
of K, the next 18-bit data word is driven onto the Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the input
clock (K and K).
These devices operate with a read latency of two and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then the device behaves in QDR I mode with
a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input and output timing
are referenced from the rising edge of the input clocks (K and K).
When the read port is deselected, the CY7C2262XV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables for a
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
Document Number : 001-70330 Rev. *B
Page 6 of 29
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