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CY7C199CN PDF预览

CY7C199CN

更新时间: 2024-12-01 05:09:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 608K
描述
256K (32K x 8) Static RAM

CY7C199CN 数据手册

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CY7C199CN  
256K (32K x 8) Static RAM  
Features  
General Description [1]  
• Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns  
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)  
• CMOS for optimum speed and power  
• TTL-compatible inputs and outputs  
• 2.0V data retention  
The CY7C199CN is a high performance CMOS Asynchronous  
SRAM organized as 32K by 8 bits that supports an  
asynchronous memory interface. The device features an  
automatic power down feature that reduces power  
consumption when deselected.  
See the “Truth Table” on page 3 in this data sheet for a  
complete description of read and write modes.  
• Low CMOS standby power  
• Automated power down when deselected  
The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin  
Molded SOJ and 28-pin DIP package(s).  
• Available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and  
28-pin DIP packages  
Logic Block Diagram  
Input Buffer  
RAM Array  
I/Ox  
CE  
WE  
OE  
Power  
Down  
Circuit  
Column Decoder  
A X  
X
Product Portfolio  
–12  
–15  
–20  
20  
–25  
25  
Unit  
ns  
Maximum Access Time  
12  
85  
15  
80  
Maximum Operating Current  
75  
75  
mA  
µA  
Maximum CMOS Standby Current  
(low power)  
500  
500  
500  
500  
Note  
1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06435 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 08, 2007  
[+] Feedback  

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