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CY7C199CN_11 PDF预览

CY7C199CN_11

更新时间: 2024-12-01 09:45:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
18页 383K
描述
256 K (32 K x 8) Static RAM 2.0 V data retention

CY7C199CN_11 数据手册

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CY7C199CN  
256 K (32 K × 8) Static RAM  
Features  
General Description [1]  
Fast access time: 15 ns and 20 ns  
Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)  
CMOS for optimum speed and power  
TTL-compatible inputs and outputs  
2.0 V data retention  
The CY7C199CN is a high performance CMOS Asynchronous  
SRAM organized as 32K by 8 bits that supports an asynchronous  
memory interface. The device features an automatic power  
down feature that reduces power consumption when deselected.  
See the “Truth Table” on page 4 in this data sheet for a complete  
description of read and write modes.  
The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin  
Molded SOJ and 28-pin DIP package(s).  
Low CMOS standby power  
Automated power down when deselected  
Available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and  
28-pin DIP packages  
Logic Block Diagram  
Input Buffer  
RAM Array  
I/Ox  
CE  
WE  
OE  
Power  
Down  
Circuit  
Column Decoder  
A X  
X
Product Portfolio  
–15  
–20  
20  
Unit  
Maximum Access Time  
15  
80  
ns  
mA  
μA  
Maximum Operating Current  
75  
Maximum CMOS Standby Current (low power)  
500  
500  
Cypress Semiconductor Corporation  
Document #: 001-06435 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 17, 2011  
[+] Feedback  

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