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CY7C185

更新时间： 2024-11-19 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 205K
描述
8K x 8 Static RAM

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CY7C185 数据手册

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185  
CY7C185  
8K x 8 Static RAM  
provided by an active LOW chip enable (CE1), an active HIGH  
chip enable (CE2), and active LOW output enable (OE) and  
three-state drivers. This device has an automatic power-down  
feature (CE1 or CE2), reducing the power consumption by 70%  
when deselected. The CY7C185 is in a standard 300-mil-wide  
DIP, SOJ, or SOIC package.  
Features  
• High speed  
— 15 ns  
• Fast tDOE  
• Low active power  
An active LOW write enable signal (WE) controls the writ-  
ing/reading operation of the memory. When CE1 and WE in-  
puts are both LOW and CE2 is HIGH, data on the eight data  
input/output pins (I/O0 through I/O7) is written into the memory  
location addressed by the address present on the address  
pins (A0 through A12). Reading the device is accomplished by  
selecting the device and enabling the outputs, CE1 and OE  
active LOW, CE2 active HIGH, while WE remains inactive or  
HIGH. Under these conditions, the contents of the location ad-  
dressed by the information on address pins are present on the  
eight data input/output pins.  
— 715 mW  
• Low standby power  
— 220 mW  
• CMOS for optimum speed/power  
• Easy memory expansion with CE1, CE2, and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
Functional Description[1]  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH. A die coat is used to insure alpha immunity.  
The CY7C185 is a high-performance CMOS static RAM orga-  
nized as 8192 words by 8 bits. Easy memory expansion is  
Logic Block Diagram  
Pin Configurations  
DIP/SOJ/SOIC  
Top View  
NC  
V
CC  
1
2
3
4
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A
WE  
CE  
4
A
5
2
A
A
3
6
A
A
2
A
1
7
5
I/O  
I/O  
0
A
8
6
7
8
9
10  
11  
12  
13  
14  
A
9
OE  
INPUT BUFFER  
A
A
A
A
0
10  
11  
12  
1
CE  
1
I/O  
7
I/O  
6
I/O  
5
I/O  
4
I/O  
3
A
1
A
2
I/O  
0
I/O  
1
I/O  
2
I/O  
I/O  
2
A
3
3
GND  
A
256 x 32 x 8  
ARRAY  
4
A
5
I/O  
I/O  
I/O  
I/O  
4
5
6
7
A
6
A
7
A
8
POWER  
DOWN  
CE  
1
COLUMN DECODER  
CE  
2
WE  
OE  
Selection Guide[2]  
7C185-15  
15  
7C185-20  
20  
7C185-25  
25  
7C185-35  
35  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
130  
110  
100  
100  
Maximum Standby Current (mA)  
40/15  
20/15  
20/15  
20/15  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
2. For military specifications, see the CY7C185A data sheet.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05043 Rev. *A  
Revised September 13, 2002  
1234567...12

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