Datasheet > CY7C185_11

CY7C185_11

更新时间： 2024-11-19 09:45:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	380K
描述
64-Kbit (8 K × 8) Static RAM CMOS for optimum speed/power

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数据手册

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CY7C185_11 数据手册

CY7C185

64-Kbit (8 K × 8) Static RAM

Features

Functional Description

■ High speed

❐ 15 ns

The CY7C185^[1]is a high-performance CMOS static RAM

organized as 8192 words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE₁), an active HIGH

chip enable (CE₂), and active LOW output enable (OE) and

tri-state drivers. This device has an automatic power-down

feature (CE₁or CE₂), reducing the power consumption by 70%

when deselected. The CY7C185 is in a standard 300-mil-wide

DIP, SOJ, or SOIC package.

■ Fast t_DOE

■ Low active power

❐ 715 mW

■ Low standby power

❐ 85 mW

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE₁and WE

inputs are both LOW and CE₂is HIGH, data on the eight data

input/output pins (I/O₀through I/O₇) is written into the memory

location addressed by the address present on the address pins

(A₀through A₁₂). Reading the device is accomplished by

selecting the device and enabling the outputs, CE₁and OE

active LOW, CE₂active HIGH, while WE remains inactive or

HIGH. Under these conditions, the contents of the location

addressed by the information on address pins are present on the

eight data input or output pins.

■ CMOS for optimum speed/power

■ Easy memory expansion with CE₁, CE₂and OE features

■ TTL-compatible inputs and outputs

■ Automatic power-down when deselected

■ Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin

(300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded

DIP

The input or output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable (WE)

is HIGH. A die coat is used to insure alpha immunity.

Logic Block Diagram

I/O

INPUT BUFFER

I/O

8K x 8

ARRAY

I/O

POWER

DOWN

COLUMN DECODER

Selection Guide

Description

-15

-20

-35

Maximum Access Time (ns)

Maximum Operating Current (mA)

130

110

100

Maximum CMOS Standby Current (mA)

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05043 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 20, 2011

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与CY7C185_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C185-10DC	CYPRESS	获取价格	Standard SRAM, 8KX8, 10ns, CMOS, CDIP28, CERDIP-28
CY7C185-10PC	CYPRESS	获取价格	Standard SRAM, 8KX8, 10ns, CMOS, PDIP28, PLASTIC, DIP-28
CY7C185-10VC	CYPRESS	获取价格	Standard SRAM, 8KX8, 10ns, CMOS, PDSO28, SOJ-28
CY7C185-10VCR	CYPRESS	获取价格	Standard SRAM, 8KX8, 10ns, CMOS, PDSO28, PLASTIC, SOJ-28
CY7C185-10VCT	CYPRESS	获取价格	Standard SRAM, 8KX8, 10ns, CMOS, PDSO28, SOJ-28
CY7C185-12DC	ETC	获取价格	x8 SRAM
CY7C185-12DMB	CYPRESS	获取价格	Standard SRAM, 8KX8, 12ns, CMOS, CDIP28
CY7C185-12LMB	CYPRESS	获取价格	Standard SRAM, 8KX8, 12ns, CMOS, CQCC28
CY7C185-12PC	CYPRESS	获取价格	8K x 8 Static RAM
CY7C185-12VC	CYPRESS	获取价格	8K x 8 Static RAM

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