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CY7C185_06 PDF预览

CY7C185_06

更新时间： 2024-11-19 04:53:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 306K
描述
8K x 8 Static RAM

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中文翻译

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CY7C185_06 数据手册

 浏览型号CY7C185_06的Datasheet PDF文件第2页浏览型号CY7C185_06的Datasheet PDF文件第3页浏览型号CY7C185_06的Datasheet PDF文件第4页浏览型号CY7C185_06的Datasheet PDF文件第5页浏览型号CY7C185_06的Datasheet PDF文件第6页浏览型号CY7C185_06的Datasheet PDF文件第7页 
1bCY7C185  
CY7C185  
8K x 8 Static RAM  
Features  
Functional Description[1]  
• High speed  
The CY7C185 is a high-performance CMOS static RAM  
organized as 8192 words by 8 bits. Easy memory expansion  
is provided by an active LOW chip enable (CE1), an active  
HIGH chip enable (CE2), and active LOW output enable (OE)  
and tri-state drivers. This device has an automatic  
power-down feature (CE1 or CE2), reducing the power  
consumption by 70% when deselected. The CY7C185 is in a  
standard 300-mil-wide DIP, SOJ, or SOIC package.  
— 15 ns  
• Fast tDOE  
• Low active power  
— 715 mW  
• Low standby power  
— 85 mW  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE1 and WE  
inputs are both LOW and CE2 is HIGH, data on the eight data  
input/output pins (I/O0 through I/O7) is written into the memory  
location addressed by the address present on the address  
pins (A0 through A12). Reading the device is accomplished by  
selecting the device and enabling the outputs, CE1 and OE  
active LOW, CE2 active HIGH, while WE remains inactive or  
HIGH. Under these conditions, the contents of the location  
addressed by the information on address pins are present on  
the eight data input/output pins.  
• CMOS for optimum speed/power  
• Easy memory expansion with CE1, CE2 and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• Available in non Pb-free 28-pin (300-Mil) Molded SOJ,  
28-pin (300-Mil) Molded SOIC and both Pb-free and non  
Pb-free in 28-pin (300-Mil) Molded DIP  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH. A die coat is used to insure alpha immunity.  
Logic Block Diagram  
Pin Configurations  
DIP/SOJ  
Top View  
I/O  
I/O  
0
INPUT BUFFER  
NC  
A
4
V
CC  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
WE  
CE  
2
3
4
5
A
5
2
A
1
I/O  
I/O  
A
A
3
2
6
A
2
A
A
2
7
A
8
A
1
A
3
6
7
8
9
3
A
9
OE  
A
8K x 8  
ARRAY  
4
A
A
A
A
0
A
10  
11  
12  
5
I/O  
4
I/O  
5
I/O  
6
I/O  
7
CE  
1
A
6
I/O  
7
I/O  
6
I/O  
5
I/O  
4
I/O  
3
10  
11  
12  
13  
14  
A
A
8
7
I/O  
0
I/O  
1
I/O  
2
GND  
POWER  
DOWN  
CE  
1
COLUMN DECODER  
CE  
2
WE  
OE  
Selection Guide  
-15  
-20  
20  
-25  
-35  
Maximum Access Time (ns)  
15  
130  
15  
25  
100  
15  
35  
Maximum Operating Current (mA)  
110  
15  
100  
15  
Maximum CMOS Standby Current (mA)  
Notes:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05043 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 24, 2006  
[+] Feedback  
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