Datasheet > CY7C1565KV18-550BZXC

CY7C1565KV18-550BZXC

更新时间： 2024-11-24 15:18:19

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
30页	760K
描述
Synchronous SRAM

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CY7C1565KV18-550BZXC 数据手册

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CY7C1565KV18

72-Mbit QDR^®II+ SRAM Four-Word

Burst Architecture (2.5 Cycle Read Latency)

72-QDR^®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.5 cycles

CY7C1565KV18: 2M × 36

■ 550-MHz clock for high bandwidth

Functional Description

■ Four-word burst for reducing address bus frequency

The CY7C1565KV18 is1.8-V synchronous pipelined SRAM,

equipped with QDR II+ architecture. Similar to QDR II

architecture, QDR II+ architecture consists of two separate ports:

the read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turnaround” the

data bus that exists with common I/O devices. Each port is

accessed through a common address bus. Addresses for read

and write addresses are latched on alternate rising edges of the

input (K) clock. Accesses to the QDR II+ read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 36-bit

words (CY7C1565KV18) that burst sequentially into or out of the

device. Because data is transferred into and out of the device on

every rising edge of both input clocks (K and K), memory

bandwidth is maximized while simplifying system design by

eliminating bus “turnarounds”.

■ Double data rate (DDR) Interfaces on both read and write ports

(data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5-clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Quaddatarate(QDR^®)II+operateswith2.5-cyclereadlatency

when DOFF is asserted HIGH

■ Operates similar to QDR I device with one cycle read latency

when DOFF is asserted LOW

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Available in × 36 configurations

■ Full data coherency, providing most current data

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

[1]

■ Core V_DD= 1.8 V± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

■ High-speed transceiver logic (HSTL) inputs and variable drive

HSTL output buffers

For a complete list of related documentation, click here.

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(13 ×15 ×1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

550 MHz

550

500 MHz

500

450 MHz

450

400 MHz Unit

Maximum operating frequency

Maximum operating current

400

MHz

× 36

1310

1210

1100

1000

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-15878 Rev. *S

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 30, 2017

12 3 4 5 6 7...30

中文翻译

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与CY7C1565KV18-550BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1565KV18-550BZXI	CYPRESS	获取价格	72-Mbit QDR-II+ SRAM 4-Word Burst Architecture
CY7C1565V18	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-300BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-300BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-300BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-300BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-333BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-333BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-333BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1565V18-333BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu

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