Datasheet > CY7C1510JV18_09

CY7C1510JV18_09

更新时间： 2024-11-24 06:51:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	634K
描述
72-Mbit QDR™-II SRAM 2-Word Burst Architecture

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数据手册

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CY7C1510JV18_09 数据手册

CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

72-Mbit QDR™-II SRAM 2-Word

Burst Architecture

Features

Configurations

■

Separate Independent Read and Write Data Ports

Supports concurrent transactions

CY7C1510JV18 – 8M x 8

CY7C1525JV18 – 8M x 9

CY7C1512JV18 – 4M x 18

CY7C1514JV18 – 2M x 36

❐

■

267 MHz Clock for High Bandwidth

2-word Burst on all Accesses

Functional Description

Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 534 MHz) at 267 MHz

The CY7C1510JV18, CY7C1525JV18, CY7C1512JV18, and

CY7C1514JV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II architecture has

separate data inputs and data outputs to eliminate the need to

‘turnaround’ the data bus that exists with common I/O devices.

Access to each port is through a common address bus.

Addresses for read and write addresses are latched on alternate

rising edges of the input (K) clock. Accesses to the QDR-II read

and write ports are completely independent of one another. To

maximize data throughput, both read and write ports are

equipped with DDR interfaces. Each address location is

associated with two 8-bit words (CY7C1510JV18), 9-bit words

(CY7C1525JV18), 18-bit words (CY7C1512JV18), or 36-bit

words (CY7C1514JV18) that burst sequentially into or out of the

device. Because data is transferred into and out of the device on

every rising edge of both input clocks (K and K and C and C),

memory bandwidth is maximized while simplifying system

design by eliminating bus ‘turnarounds’.

■

Two Input Clocks (K and K) for Precise DDR Timing

❐

SRAM uses rising edges only

Two Input Clocks for Output Data (C and C) to Minimize Clock

Skew and Flight Time Mismatches

EchoClocks(CQandCQ)SimplifyDataCaptureinHighSpeed

Systems

Single Multiplexed Address Input Bus Latches Address Inputs

for both Read and Write Ports

■

Separate Port Selects for Depth Expansion

Synchronous Internally Self-timed Writes

QDR-II Operates with 1.5 Cycle Read Latency when Delay

Lock Loop (DLL) is enabled

■

Operates like a QDR-I Device with 1 Cycle Read Latency in

DLL Off Mode

■

Available in x8, x9, x18, and x36 Configurations

Full Data Coherency, providing most current data

Core V_DD= 1.8V (±0.1V); I/O V_DDQ= 1.4V to V_DD

Available in 165-Ball FBGA Package (15 x 17 x 1.4 mm)

Offered in both Pb-free and non Pb-free Packages

Variable Drive HSTL Output Buffers

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

JTAG 1149.1 Compatible Test Access Port

Delay Lock Loop (DLL) for Accurate Data Placement

Selection Guide

Description

267 MHz

267

250 MHz

250

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

1375

1385

1495

1710

1245

1255

1365

1580

x18

x36

Cypress Semiconductor Corporation

Document #: 001-14435 Rev. *F

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised July 31, 2009

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与CY7C1510JV18_09相关器件

型号	品牌	获取价格	描述	数据表
CY7C1510JV18-250BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-250BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-250BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-250BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZXC	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510JV18-267BZXI	CYPRESS	获取价格	72-Mbit QDR⑩-II SRAM 2-Word Burst Architectur
CY7C1510KV18	CYPRESS	获取价格	72-Mbit QDR II SRAM 2-Word Burst Architecture Two-word burst on all accesses
CY7C1510KV18_09	CYPRESS	获取价格	72-Mbit QDR-II SRAM 2-Word Burst Architecture

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