CY7C1510JV18, CY7C1525JV18
CY7C1512JV18, CY7C1514JV18
Document History Page
Document Title: CY7C1510JV18/CY7C1525JV18/CY7C1512JV18/CY7C1514JV18, 72-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Document Number: 001-14435
Orig. Of
Change
Submission
Date
Rev. ECN No.
Description Of Change
**
1060980
1397384
1462588
VKN
VKN
See ECN
See ECN
See ECN
New Data Sheet
*A
*B
Added 267MHz speed bin
VKN/AESA
Converted from preliminary to final
Removed 200MHz speed bin
Updated IDD/ISB specs
Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed tCYC max spec to 8.4ns for all speed bins
*C
*D
2189567
2561954
VKN/AESA
VKN/PYRS
See ECN
09/04/08
Minor Change-Moved to the external web
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to
“–55°C to +125°C” in the “Maximum Ratings“ on page 20,
Updated Power-up sequence waveform and it’s description,
Added footnote #19 related to IDD
,
Changed ΘJA spec from 16.2 to 16.3, Changed ΘJC spec from 2.3 to 2.1,
Changed JTAG ID [31:29] from 001 to 000.
*E
*F
2612311
2746930
VKN/PYRS
NJY
11/25/08
07/31/09
Corrected logic block diagram of CY7C1525JV18
Post to external web
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Document #: 001-14435 Rev. *F
Revised July 31, 2009
Page 26 of 26
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
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