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CY7C1510AV18-200BZXC PDF预览

CY7C1510AV18-200BZXC

更新时间： 2024-01-31 08:07:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
26页 1098K
描述
72-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture

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CY7C1510AV18-200BZXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：200 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：17 mm内存密度：67108864 bit
内存集成电路类型：QDR SRAM内存宽度：8
湿度敏感等级：3功能数量：1
端子数量：165字数：8388608 words
字数代码：8000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：8MX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：0.38 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：1.01 mA
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：15 mm
Base Number Matches：1

CY7C1510AV18-200BZXC 数据手册

 浏览型号CY7C1510AV18-200BZXC的Datasheet PDF文件第4页浏览型号CY7C1510AV18-200BZXC的Datasheet PDF文件第5页浏览型号CY7C1510AV18-200BZXC的Datasheet PDF文件第6页浏览型号CY7C1510AV18-200BZXC的Datasheet PDF文件第8页浏览型号CY7C1510AV18-200BZXC的Datasheet PDF文件第9页浏览型号CY7C1510AV18-200BZXC的Datasheet PDF文件第10页 
CY7C1510AV18  
CY7C1525AV18  
CY7C1512AV18  
CY7C1514AV18  
PRELIMINARY  
Pin Definitions (continued)  
Pin Name  
I/O  
Pin Description  
K
Input-Clock  
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs  
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses  
are initiated on the rising edge of K.  
K
Input-Clock  
Echo Clock  
Negative Input Clock Input. K is used to capture synchronous inputs being presented  
to the device and to drive out data through Q[x:0] when in single clock mode.  
CQ  
CQ is referenced with respect to C. This is a free running clock and is synchronized  
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is  
generated with respect to K. The timings for the echo clocks are shown in the AC Timing  
table.  
CQ  
ZQ  
CQ is referenced with respect to C. This is a free running clock and is synchronized  
to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is  
generated with respect to K. The timings for the echo clocks are shown in the AC Timing  
table.  
Echo Clock  
Input  
Output Impedance Matching Input. This input is used to tune the device outputs to the  
system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ,  
where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be  
connected directly to VDDQ, which enables the minimum impedance mode. This pin  
cannot be connected directly to GND or left unconnected.  
DOFF  
Input  
DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside  
the device. The timings in the DLL turned off operation will be different from those listed  
in this data sheet. For normal operation, this pin can be connected to a pull-up through  
a 10-Kohm or less pull-up resistor. The device will behave in QDR-I mode when the DLL  
is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz  
with QDR-I timing.  
TDO  
Output  
Input  
Input  
Input  
N/A  
TDO for JTAG.  
TCK  
TCK pin for JTAG.  
TDI  
TDI pin for JTAG.  
TMS  
TMS pin for JTAG.  
NC  
Not connected to the die. Can be tied to any voltage level.  
Address expansion for 144M. Can be tied to any voltage level.  
Address expansion for 288M. Can be tied to any voltage level.  
VSS /144M  
VSS / 288M  
VREF  
Input  
Input  
Input-  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs  
Reference  
and Outputs as well as AC measurement points.  
VDD  
VSS  
Power Supply  
Ground  
Power supply inputs to the core of the device.  
Ground for the device.  
VDDQ  
Power Supply  
Power supply inputs for the outputs of the device.  
CY7C1512AV18 and two 36-bit data transfers in the case of  
CY7C1514AV18, in one clock cycle.  
Functional Overview  
The CY7C1510AV18,CY7C1525AV18,CY7C1512AV18 and  
CY7C1514AV18 are synchronous pipelined Burst SRAMs  
equipped with both a Read port and a Write port. The Read  
port is dedicated to Read operations and the Write port is  
dedicated to Write operations. Data flows into the SRAM  
through the Write port and out through the Read Port. These  
devices multiplex the address inputs in order to minimize the  
number of address pins required. By having separate Read  
and Write ports, the QDR-II completely eliminates the need to  
“turn-around” the data bus and avoids any possible data  
contention, thereby simplifying system design. Each access  
consists of two 8-bit data transfers in the case of  
CY7C1510AV18, two 9-bit data transfers in the case of  
CY7C1525AV18, two 18-bit data transfers in the case of  
This device operates with a read latency of one and half cycles  
when DOFF pin is tied HIGH. When DOFF pin is set LOW or  
connected to VSS then the device will behave in QDR-I mode  
with a read latency of one clock cycle.  
Accesses for both ports are initiated on the rising edge of the  
positive Input Clock (K). All synchronous input timings are  
referenced from the rising edge of the input clocks (K and K)  
and all output timings are referenced to the rising edge of  
output clocks (C and C or K and K when in single clock mode).  
All synchronous data inputs (D[x:0]) inputs pass through input  
registers controlled by the input clocks (K and K). All  
synchronous data outputs (Q[x:0]) outputs pass through output  
Document #: 001-06984 Rev. *B  
Page 7 of 26  
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