Datasheet > CY7C1461V33-133BZC

CY7C1461V33-133BZC

更新时间： 2024-01-27 04:22:20

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
26页	472K
描述
ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1461V33-133BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.20 MM HEIGHT, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	6.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	37748736 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大待机电流：	0.015 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	15 mm	Base Number Matches：	1

CY7C1461V33-133BZC 数据手册

浏览型号CY7C1461V33-133BZC的Datasheet PDF文件第2页

浏览型号CY7C1461V33-133BZC的Datasheet PDF文件第3页

浏览型号CY7C1461V33-133BZC的Datasheet PDF文件第4页

浏览型号CY7C1461V33-133BZC的Datasheet PDF文件第5页

浏览型号CY7C1461V33-133BZC的Datasheet PDF文件第6页

CY7C1461V33

CY7C1463V33

CY7C1465V33

PRELIMINARY

1Mx36/2Mx18/512Kx72Flow-ThruSRAM

with NoBL™ Architecture

BWS_c,BWS_d,BWS_e, BWS_f, BWS_g, BWS_h), and Read-Write

control (WE). BWS_cand BWS_dapply to CY7C1461V33 and

CY7C1465V33 only. BWS_e, BWS_f,BWS_gand BWS_happly to

CY7C1465V33 only

Features

• Zero Bus Latency , no dead cycles between Write and

Read cycles

•Supports 133-MHz bus operations

•1M × 36/2M × 18/512K × 72 common I/O

•Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

Clock Enable (CEN) pin allows operation of the

CY7C1461V33, CY7C1463V33, and CY7C1465V33 to be

suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers

will hold their previous values.

There are three Chip Enable (CE₁, CE₂, CE₃) pins that allow

the user to deselect the device when desired. If any one of

these three are not active when ADV/LD is low, no new

memory operation can be initiated and any burst cycle in

progress is stopped. However, any pending data transfers

(READ or WRITE) will be completed. The data bus will be in

high impedance state two cycles after chip is deselected or a

Write cycle is initiated.

• Single 3.3V –5% and +5% power supply V_DD

• Separate V_DDQfor 3.3V or 2.5V

• Clock Enable (CEN) pin to suspend operation

• Burst Capability–linear or interleaved burst order

• Available in 119-ball bump BGA, 165-ball FBGA, and

100-pin TQFP packages (CY7C1461V33 and

CY7C1463V33). 209-ball FBGA package for

CY7C1465V33.

The CY7C1461V33, CY7C1463V33 and CY7C1465V33 have

an on-chip two-bit burst counter. In the burst mode,

CY7C1461V33, CY7C1463V33 and CY7C1465V33 provide

four cycles of data for a single address presented to the

SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load

a new external address (ADV/LD = LOW) or increment the

internal burst counter (ADV/LD = HIGH)

Functional Description

The CY7C1461V33, CY7C1463V33 and CY7C1465V33

SRAMs are designed to eliminate dead cycles when transi-

tions from Read to Write or vice versa. These SRAMs are

optimized for 100% bus utilization and achieve Zero Bus

Latency. They integrate 1,048,576 × 36/2,097,152 × 18/

524,288 × 72 SRAM cells, respectively, with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. The Synchronous Burst SRAM family

employs high-speed, low-power CMOS designs using

advanced single layer polysilicon, threelayer metal

technology. Each memory cell consists of six transistors.

Output Enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the

outputs at any given time. ZZ may be tied to LOW if it is not

used.

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, depth-expansion

Chip Enables (CE₁, CE₂and CE₃), cycle start input (ADV/LD),

Clock Enable (CEN), Byte Write Selects (BWS_a, BWS_b,

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

CEN

CONTROL

and WRITE

LOGIC

1M × 36

2M × 18

512K × 72

Memory

Array

BWS

X = a, b

, c, d

X= a, b,

c, d

X = a, b,

c, d

X = 19:0

X = 20:0

1M×36

Mode

X = a, b

X = a, b X = a, b

2M×18

X = a, b

X = a, b,

c,d,e,f,g,h

X = 18:0

512K×72

c,d,e,f,g,h

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05193 Rev. *B

Revised November 18, 2002

12 3 4 5 6 7...26

下载PDF

与CY7C1461V33-133BZC相关器件

型号	品牌	描述	获取价格	数据表
CY7C1461V33-150BGC	CYPRESS	ZBT SRAM, 1MX36, 5.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	获取价格
CY7C1461V33-150BZC	CYPRESS	ZBT SRAM, 1MX36, 5.5ns, CMOS, PBGA165, 15 X 17 MM, 1.20 MM HEIGHT, FBGA-165	获取价格
CY7C146-25JC	CYPRESS	2Kx8 Dual-Port Static RAM	获取价格
CY7C146-25JCR	CYPRESS	Multi-Port SRAM, 2KX8, 25ns, CMOS, PQCC52, PLASTIC, LCC-52	获取价格
CY7C146-25JCT	CYPRESS	Dual-Port SRAM, 2KX8, 25ns, CMOS, PQCC52, PLASTIC, LCC-52	获取价格
CY7C146-25JXC	CYPRESS	2K x 8 Dual-Port Static RAM	获取价格

与CY7C1461V33-133BZC相关文章

MAX7219驱动8段数码管详解及数据手册关键信息
2024-05-29

5
ATMEGA328P技术资料深入分析
2024-05-29

3
AT24C02芯片手册管脚信息、参数分析、应用领域详解
2024-05-29

4
AT24C256芯片手册参数分析、引脚说明、读写程序示例
2024-05-28

6

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1461V33-133BZC

CY7C1461V33-133BZC 技术参数

CY7C1461V33-133BZC 数据手册

与CY7C1461V33-133BZC相关器件

与CY7C1461V33-133BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1461V33-133BZC

CY7C1461V33-133BZC 技术参数

CY7C1461V33-133BZC 数据手册

与CY7C1461V33-133BZC相关器件

与CY7C1461V33-133BZC相关文章

您还可以找

您在本页遇到什么问题？