CY7C1461V33
CY7C1463V33
CY7C1465V33
PRELIMINARY
1Mx36/2Mx18/512Kx72Flow-ThruSRAM
with NoBL™ Architecture
BWSc,BWSd,BWSe, BWSf, BWSg, BWSh), and Read-Write
control (WE). BWSc and BWSd apply to CY7C1461V33 and
CY7C1465V33 only. BWSe, BWSf, BWSg and BWSh apply to
CY7C1465V33 only
Features
• Zero Bus Latency , no dead cycles between Write and
Read cycles
•Supports 133-MHz bus operations
•1M × 36/2M × 18/512K × 72 common I/O
•Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.5 ns (for 117-MHz device)
A
Clock Enable (CEN) pin allows operation of the
CY7C1461V33, CY7C1463V33, and CY7C1465V33 to be
suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers
will hold their previous values.
There are three Chip Enable (CE1, CE2, CE3) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is low, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(READ or WRITE) will be completed. The data bus will be in
high impedance state two cycles after chip is deselected or a
Write cycle is initiated.
• Single 3.3V –5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V
• Clock Enable (CEN) pin to suspend operation
• Burst Capability–linear or interleaved burst order
• Available in 119-ball bump BGA, 165-ball FBGA, and
100-pin TQFP packages (CY7C1461V33 and
CY7C1463V33). 209-ball FBGA package for
CY7C1465V33.
The CY7C1461V33, CY7C1463V33 and CY7C1465V33 have
an on-chip two-bit burst counter. In the burst mode,
CY7C1461V33, CY7C1463V33 and CY7C1465V33 provide
four cycles of data for a single address presented to the
SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD = LOW) or increment the
internal burst counter (ADV/LD = HIGH)
Functional Description
The CY7C1461V33, CY7C1463V33 and CY7C1465V33
SRAMs are designed to eliminate dead cycles when transi-
tions from Read to Write or vice versa. These SRAMs are
optimized for 100% bus utilization and achieve Zero Bus
Latency. They integrate 1,048,576 × 36/2,097,152 × 18/
524,288 × 72 SRAM cells, respectively, with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. The Synchronous Burst SRAM family
employs high-speed, low-power CMOS designs using
advanced single layer polysilicon, threelayer metal
technology. Each memory cell consists of six transistors.
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE1, CE2 and CE3), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Selects (BWSa, BWSb,
Logic Block Diagram
D
CLK
Data-In REG.
CE
Q
ADV/LD
A
x
CEN
CE
CONTROL
and WRITE
LOGIC
1M × 36
1
2M × 18
CE
2
512K × 72
Memory
Array
DQ
x
CE
DQ
3
A
BWS
X
DP
X
X
X
DP
WE
x
BWS
X = a, b
, c, d
x
X= a, b,
c, d
X = a, b,
c, d
X = 19:0
X = 20:0
1M×36
Mode
X = a, b
X = a, b X = a, b
2M×18
X = a, b
X = a, b,
X = a, b,
c,d,e,f,g,h
c,d,e,f,g,h
X = 18:0
512K×72
OE
c,d,e,f,g,h
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05193 Rev. *B
Revised November 18, 2002
5秒后页面跳转
MAX7219驱动8段数码管详解及数据手册关键信息
ATMEGA328P技术资料深入分析
AT24C02芯片手册管脚信息、参数分析、应用领域详解
AT24C256芯片手册参数分析、引脚说明、读写程序示例
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
