Datasheet > CY7C1424BV18

CY7C1424BV18

更新时间： 2024-11-05 05:19:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
28页	1159K
描述
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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CY7C1424BV18 数据手册

CY7C1422BV18

CY7C1429BV18

CY7C1423BV18

CY7C1424BV18

PRELIMINARY

36-Mbit DDR-II SIO SRAM 2-Word Burst

Architecture

Features

Functional Description

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

• 300-MHz clock for high bandwidth

The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18 and

CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II SIO (Double Data Rate Separate I/O)

architecture. The DDR-II SIO consists of two separate ports to

access the memory array. The Read port has dedicated Data

outputs and the Write port has dedicated Data inputs to

completely eliminate the need to “turn around’ the data bus

required with common I/O devices. Access to each port is

accomplished using a common address bus. Addresses for

Read and Write are latched on alternate rising edges of the

input (K) clock. Write data is registered on the rising edges of

both K and K. Read data is driven on the rising edges of C and

C if provided, or on the rising edge of K and K if C/C are not

provided. Each address location is associated with two 8-bit

words in the case of CY7C1422BV18, two 9-bit words in the

case of CY7C1429BV18, two 18-bit words in the case of

CY7C1423BV18, and two 36-bit words in the case of

CY7C1424BV18, that burst sequentially into or out of the

device.

• 2-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• DDR-II operates with 1.5 cycle read latency when DLL

is enabled

• Operates like a DDR I device with 1 cycle read latency

in DLL off mode

Asynchronous inputs include output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to

the two output echo clocks CQ/CQ, eliminating the need for

separately capturing data from each individual DDR-II SIO

SRAM in the system design. Output data clocks (C/C) enable

maximum system clocking and data synchronization flexibility.

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V_DD

)

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• JTAG 1149.1 compatible test access port

All synchronous inputs pass through input registers controlled

by the K/K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clock. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• Delay Lock Loop (DLL) for accurate data placement

Configuration

CY7C1422BV18–4M x 8

CY7C1429BV18–4M x 9

CY7C1423BV18–2M x18

CY7C1424BV18–1M x 36

Selection Guide

300 MHz

300

278 MHz

250 MHz

250

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

278

775

825

700

600

500

Cypress Semiconductor Corporation

Document Number: 001-07035 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 20, 2006

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与CY7C1424BV18相关器件

型号	品牌	获取价格	描述	数据表
CY7C1424BV18-167BZC	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-167BZI	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-167BZXC	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-167BZXI	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-200BZC	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-200BZI	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-200BZXC	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-200BZXI	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-250BZC	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1424BV18-250BZI	CYPRESS	获取价格	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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