Datasheet > CY7C1412AV18-200BZC

CY7C1412AV18-200BZC

更新时间： 2024-11-30 05:19:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
23页	266K
描述
36-Mbit QDR-II⑩ SRAM 2-Word Burst Architecture

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CY7C1410AV18

CY7C1425AV18

CY7C1412AV18

CY7C1414AV18

PRELIMINARY

36-Mbit QDR-II™ SRAM 2-Word

Burst Architecture

Features

Functional Description

• Separate Independent Read and Write data ports

The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and

CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. The Read address is latched on the

rising edge of the K clock and the Write address is latched on

the rising edge of the K clock. Accesses to the QDR-II Read

and Write ports are completely independent of one another. In

order to maximize data throughput, both Read and Write ports

are equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with two 8-bit words

(CY7C1410AV18) or 9-bit words (CY7C1425AV18) or 18-bit

words (CY7C1412AV18) or 36-bit words (CY7C1414AV18)

that burst sequentially into or out of the device. Since data can

be transferred into and out of the device on every rising edge

of both input clocks (K and K and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

— Supports concurrent transactions

• 200-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 400 MHz) @ 200 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency, providing most current data

• Core V_DD= 1.8V (±0.1V); I/O V_DDQ= 1.4V to V_DD

• 15 × 17 × 1.4 mm 1.0-mm pitch FBGA package, 165-ball

(11 × 15 matrix)

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1410AV18 – 4M x 8

CY7C1425AV18 – 4M x 9

CY7C1412AV18 – 2M x 18

CY7C1414AV18 – 1M x 36

Selection Guide

250 MHz

200 MHz

200

167 MHz

167

Unit

MHz

Maximum Operating Frequency

250

Maximum Operating Current

TBD

Shaded areas contain advance information.

Please contact your local Cypress Sales representative for availability of these parts.

Cypress Semiconductor Corporation

Document #: 38-05615 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 06, 2004

12 3 4 5 6 7...23

中文翻译

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CY7C1412AV18-200BZC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1412AV18-200BZXC	CYPRESS	功能相似	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur

与CY7C1412AV18-200BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1412AV18-200BZI	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412AV18-200BZXC	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412AV18-200BZXI	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412AV18-250BZC	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412AV18-250BZI	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412AV18-250BZXC	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412AV18-250BZXI	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412BV18	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur
CY7C1412BV18-167BZC	CYPRESS	获取价格	36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1412BV18-167BZI	CYPRESS	获取价格	36-Mbit QDR-II⑩ SRAM 2-Word Burst Architectur

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