Datasheet > CY7C1386KV33-167AXC

CY7C1386KV33-167AXC

更新时间： 2024-11-26 01:03:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
23页	390K
描述
18-Mbit (512K Ã 36/1M Ã 18) Pipelined DCD Sync SRAM

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CY7C1386KV33

CY7C1387KV33

18-Mbit (512K × 36/1M × 18)

Pipelined DCD Sync SRAM

18-Mbit (512K

× 36/1M × 18) Pipelined DCD Sync SRAM

Features

Functional Description

■ Supports bus operation up to 200 MHz

The CY7C1386KV33/CY7C1387KV33 SRAM integrates

512K × 36/1M × 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive edge triggered clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining chip enable (CE₁), depth expansion chip

■ Available speed grades are 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ Optimal for performance (double-cycle deselect)

■ Depth expansion without wait state

enables (CE and CE ), burst control inputs (ADSC, ADSP,

and

■ 3.3 V core power supply (V_DD

)

ADV), write enables ( , and BWE), and global write (GW).

BW_X

Asynchronous inputs include the output enable (OE) and the ZZ

pin.

■ 2.5 V or 3.3 V I/O power supply (V_DDQ)

■ Fast clock-to-output times

❐ 3 ns (for 200 MHz device)

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

■ Provides high performance 3-1-1-1 access rate

■ User selectable burst counter supporting interleaved or linear

burst sequences

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Configurations on page 5 and Truth Table on

page 9 for further details). Write cycles can be one to four bytes

wide as controlled by the byte write control inputs. GW active

LOW causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off the

■ Separate processor and controller address strobes

■ Synchronous self-timed writes

■ Asynchronous output enable

■ CY7C1386KV33 available in JEDEC-standard Pb-free 100-pin

TQFP. CY7C1387KV33 available in JEDEC-standard Pb-free

100-pin TQFP

output buffers an additional cycle when

a deselect is

executed.This feature allows depth expansion without penalizing

system performance.

■ ZZ sleep mode option

The CY7C1386KV33/CY7C1387KV33 operates from a +3.3 V

core power supply while all outputs operate with a +3.3 V or

+2.5 V supply. All inputs and outputs are JEDEC-standard and

JESD8-5-compatible.

Selection Guide

Description

Maximum access time

200 MHz

3.0

167 MHz Unit

3.4

143

163

Maximum operating current

× 18

× 36

158

178

Cypress Semiconductor Corporation

Document Number: 001-97893 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 8, 2018

12 3 4 5 6 7...23

中文翻译

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CY7C1386KV33-167AXC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1386D-167AXC	CYPRESS	完全替代	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

与CY7C1386KV33-167AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1386KV33-200AXC	CYPRESS	获取价格	18-Mbit (512K Ã 36/1M Ã 18) Pipelined DCD S
CY7C1387B	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1387B-133AC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1387B-133AI	CYPRESS	获取价格	Cache SRAM, 1MX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387B-133BGC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1387B-133BGI	CYPRESS	获取价格	暂无描述
CY7C1387B-133BZC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1387B-150AC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined DCD SRAM
CY7C1387B-150AI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387B-150BGC	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined DCD SRAM

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