Datasheet > CY7C1387BV25-150BGI

CY7C1387BV25-150BGI

更新时间： 2024-11-25 15:41:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	807K
描述
Cache SRAM, 1MX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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CY7C1387BV25-150BGI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	针数：	119
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Base Number Matches：	1

CY7C1387BV25-150BGI 数据手册

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CY7C1387BV25

CY7C1386BV25

512K x 36 / 1M x 18 Pipelined DCD SRAM

registers controlled by a positive-edge-triggered clock input

(CLK). The synchronous inputs include all addresses, all data

Features

• Fast clock speed: 200,167, 150, 133 MHz

• Provide high-performance 3-1-1-1 access rate

• Fast OE access times: 3.0, 3.4, 3.8, 4.2 ns

• Optimal for depth expansion

• 2.5V ± 5% power supply

• Common data inputs and data outputs

• Double-cycle Deselect

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst

sequence)

inputs, address-pipelining Chip Enable (CE), burst control

inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,

BWc, BWd and BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and burst

mode control (MODE). The data (DQ_a,b,c,d) and the data parity

(DP_a,b,c,d) outputs, enabled by OE, are also asynchronous.

DQ_a,b,c,dand DP_a,b,c,dapply to CY7C1386BV25 and DQ_a,b

and DP_a,bapply to CY7C1387BV25. a, b, c, d each are of eight

bits wide in the case of DQ and one bit wide in the case of DP.

Addresses and chip enables are registered with either address

status processor (ADSP) or address status controller (ADSC)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa and DPa. BWb controls DQb and DPb. BWc

controls DQc and DPd. BWd controls DQd-DQd and DPd.

BWa, BWb BWc, and BWd can be active only with BWE being

LOW. GW being LOW causes all bytes to be written. Write

pass-through capability allows written data available at the

output for the immediately next Read cycle. This device also

incorporates pipelined enable circuit for easy depth expansion

without penalizing system performance.

• Automatic power-down available using ZZ mode or CE

deselect

• High-density, high-speed packages

• JTAG boundary scan for BGA packaging version

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

single-layer polysilicon, triple-layer metal technology. Each

memory cell consists of six transistors.

The CY7C1386BV25 and CY7C1387BV25 SRAMs integrate

1,048,576 × 18 and 524,288 × 36 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

The CY7C1386BV25/CY7C1387BV25 are both double-cycle

deselect parts. All inputs and outputs of the CY7C1386BV25

and the CY7C1387BV25 are JEDEC-standard JESD8-5-

compatible.

Selection Guide

200 MHz

167 MHz

3.4

150 MHz

3.8

133 MHz

4.2

Unit

Maximum Access Time

3.0

280

Maximum Operating Current

Maximum CMOS Standby Current

Commercial

230

190

160

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05253 Rev. *A

Revised January 18, 2003

12 3 4 5 6 7...28

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与CY7C1387BV25-150BGI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1387BV25-150BZC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1387BV25-150BZI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1387BV25-166AC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387BV25-166BGC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387BV25-167AC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387BV25-167BGC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387BV25-167BGC	ROCHESTER	获取价格	1MX18 CACHE SRAM, 3.4ns, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387BV25-167BGI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1387BV25-200AC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387BV25-200BGC	CYPRESS	获取价格	Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119

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