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CY7C1387BV25-167AC PDF预览

CY7C1387BV25-167AC

更新时间： 2024-11-25 15:41:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
28页 807K
描述
Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1387BV25-167AC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.69最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：167 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：2.5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：2.38 V子类别：SRAMs
最大压摆率：0.23 mA最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

CY7C1387BV25-167AC 数据手册

 浏览型号CY7C1387BV25-167AC的Datasheet PDF文件第2页浏览型号CY7C1387BV25-167AC的Datasheet PDF文件第3页浏览型号CY7C1387BV25-167AC的Datasheet PDF文件第4页浏览型号CY7C1387BV25-167AC的Datasheet PDF文件第5页浏览型号CY7C1387BV25-167AC的Datasheet PDF文件第6页浏览型号CY7C1387BV25-167AC的Datasheet PDF文件第7页 
CY7C1387BV25  
CY7C1386BV25  
512K x 36 / 1M x 18 Pipelined DCD SRAM  
registers controlled by a positive-edge-triggered clock input  
(CLK). The synchronous inputs include all addresses, all data  
Features  
• Fast clock speed: 200,167, 150, 133 MHz  
• Provide high-performance 3-1-1-1 access rate  
• Fast OE access times: 3.0, 3.4, 3.8, 4.2 ns  
• Optimal for depth expansion  
• 2.5V ± 5% power supply  
• Common data inputs and data outputs  
• Double-cycle Deselect  
• Byte Write Enable and Global Write control  
• Chip enable for address pipeline  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst  
sequence)  
inputs, address-pipelining Chip Enable (CE), burst control  
inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,  
BWc, BWd and BWE), and global write (GW).  
Asynchronous inputs include the output enable (OE) and burst  
mode control (MODE). The data (DQa,b,c,d) and the data parity  
(DPa,b,c,d) outputs, enabled by OE, are also asynchronous.  
DQa,b,c,d and DPa,b,c,d apply to CY7C1386BV25 and DQa,b  
and DPa,b apply to CY7C1387BV25. a, b, c, d each are of eight  
bits wide in the case of DQ and one bit wide in the case of DP.  
Addresses and chip enables are registered with either address  
status processor (ADSP) or address status controller (ADSC)  
input pins. Subsequent burst addresses can be internally  
generated as controlled by the burst advance pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the write control inputs.  
Individual byte write allows individual byte to be written. BWa  
controls DQa and DPa. BWb controls DQb and DPb. BWc  
controls DQc and DPd. BWd controls DQd-DQd and DPd.  
BWa, BWb BWc, and BWd can be active only with BWE being  
LOW. GW being LOW causes all bytes to be written. Write  
pass-through capability allows written data available at the  
output for the immediately next Read cycle. This device also  
incorporates pipelined enable circuit for easy depth expansion  
without penalizing system performance.  
• Automatic power-down available using ZZ mode or CE  
deselect  
• High-density, high-speed packages  
• JTAG boundary scan for BGA packaging version  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced  
single-layer polysilicon, triple-layer metal technology. Each  
memory cell consists of six transistors.  
The CY7C1386BV25 and CY7C1387BV25 SRAMs integrate  
1,048,576 × 18 and 524,288 × 36 SRAM cells with advanced  
synchronous peripheral circuitry and a two-bit counter for  
internal burst operation. All synchronous inputs are gated by  
The CY7C1386BV25/CY7C1387BV25 are both double-cycle  
deselect parts. All inputs and outputs of the CY7C1386BV25  
and the CY7C1387BV25 are JEDEC-standard JESD8-5-  
compatible.  
Selection Guide  
200 MHz  
167 MHz  
3.4  
150 MHz  
3.8  
133 MHz  
4.2  
Unit  
ns  
Maximum Access Time  
3.0  
280  
30  
Maximum Operating Current  
Maximum CMOS Standby Current  
Commercial  
230  
190  
160  
mA  
mA  
30  
30  
30  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05253 Rev. *A  
Revised January 18, 2003  
1234567...28

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与CY7C1387BV25-167AC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1387BV25-167BGC CYPRESS

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 		Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387BV25-167BGC ROCHESTER

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 		1MX18 CACHE SRAM, 3.4ns, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387BV25-167BGI CYPRESS

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 		Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1387BV25-200AC CYPRESS

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 		Cache SRAM, 1MX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1387BV25-200BGC CYPRESS

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 		Cache SRAM, 1MX18, 3ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
CY7C1387BV25-200BZC CYPRESS

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 		Cache SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1387C CYPRESS

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 		18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-167AC CYPRESS

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 		18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-167AI CYPRESS

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 		18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
CY7C1387C-167BGC CYPRESS

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 		18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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