Datasheet > 存储 > SRAM> CY7C1381C-100AI

CY7C1381C-100AI

更新时间： 2024-11-26 22:34:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
36页	563K
描述
18-Mb (512K x 36/1M x 18) Flow-Through SRAM

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CY7C1381C-100AI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：	100	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.62	Is Samacsys：	N
最长访问时间：	8.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	18874368 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.07 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.175 mA
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD (800)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

CY7C1381C-100AI 数据手册

CY7C1381C

CY7C1383C

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 512K X 36/1M X 18 common I/O

The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and 1M x

18 Synchronous Flowthrough SRAMs, respectively designed

to interface with high-speed microprocessors with minimum

glue logic. Maximum access delay from clock rise is 6.5 ns

(133-MHz version). A 2-bit on-chip counter captures the first

address in a burst and increments the address automatically

for the rest of the burst access. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

• 3.3V –5% and +10% core power supply (V_DD

)

• 2.5V or 3.3V I/O supply (V_DDQ

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

)

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

addresses, all data inputs, address-pipelining Chip Enable

[2]

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

• Provide high-performance 2-1-1-1 access rate

CE₁

Control inputs (

), Write Enables

(

ADV

BW_x

• User-selectable burst counter supporting Intel^

and

ADSC ADSP

Pentium^interleaved or linear burst sequences

), and Global Write (

BWE

). Asynchronous

and

inputs

(

)

and the ZZ pin

include the Output Enable

• Separate processor and controller address strobes

• Synchronous self-timed write

The CY7C1381C/CY7C1383C allows either interleaved or

linear burst sequences, selected by the MODE input pin. A

HIGH selects an interleaved burst sequence, while a LOW

selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

• Asynchronous output enable

• OfferedinJEDEC-standard100-pinTQFP,119-ballBGA

and 165-ball fBGA packages

• JTAG boundary scan for BGA and fBGA packages

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

The CY7C1381C/CY7C1383C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

117 MHz

7.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

6.5

210

190

175

Maximum CMOS Standby Current

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05238 Rev. *B

Revised February 26, 2004

12 3 4 5 6 7...36

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与CY7C1381C-100AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1381C-100BGC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-100BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-100BGIT	CYPRESS	获取价格	Standard SRAM, 512KX36, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1381C-100BZC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-100BZI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117AC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117AI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117BGC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117BZC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM

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