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CY7C1381C-133BGC PDF预览

CY7C1381C-133BGC

更新时间： 2024-11-26 22:36:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
36页 563K
描述
18-Mb (512K x 36/1M x 18) Flow-Through SRAM

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中文翻译

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CY7C1381C-133BGC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.8最长访问时间：6.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：STANDARD SRAM
内存宽度：36功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.07 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.21 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1381C-133BGC 数据手册

 浏览型号CY7C1381C-133BGC的Datasheet PDF文件第2页浏览型号CY7C1381C-133BGC的Datasheet PDF文件第3页浏览型号CY7C1381C-133BGC的Datasheet PDF文件第4页浏览型号CY7C1381C-133BGC的Datasheet PDF文件第5页浏览型号CY7C1381C-133BGC的Datasheet PDF文件第6页浏览型号CY7C1381C-133BGC的Datasheet PDF文件第7页 
CY7C1381C  
CY7C1383C  
18-Mb (512K x 36/1M x 18) Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 133-MHz bus operations  
• 512K X 36/1M X 18 common I/O  
The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and 1M x  
18 Synchronous Flowthrough SRAMs, respectively designed  
to interface with high-speed microprocessors with minimum  
glue logic. Maximum access delay from clock rise is 6.5 ns  
(133-MHz version). A 2-bit on-chip counter captures the first  
address in a burst and increments the address automatically  
for the rest of the burst access. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
• 3.3V –5% and +10% core power supply (VDD  
)
• 2.5V or 3.3V I/O supply (VDDQ  
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
)
— 7.5 ns (117-MHz version)  
— 8.5 ns (100-MHz version)  
addresses, all data inputs, address-pipelining Chip Enable  
[2]  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
• Provide high-performance 2-1-1-1 access rate  
CE1  
2
Control inputs (  
,
,
), Write Enables  
(
ADV  
BWx  
• User-selectable burst counter supporting Intel  
and  
,
ADSC ADSP  
Pentiuminterleaved or linear burst sequences  
), and Global Write (  
BWE  
). Asynchronous  
GW  
and  
inputs  
(
)
and the ZZ pin  
OE  
.
include the Output Enable  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
The CY7C1381C/CY7C1383C allows either interleaved or  
linear burst sequences, selected by the MODE input pin. A  
HIGH selects an interleaved burst sequence, while a LOW  
selects a linear burst sequence. Burst accesses can be  
initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement  
(ADV) input.  
• Asynchronous output enable  
• OfferedinJEDEC-standard100-pinTQFP,119-ballBGA  
and 165-ball fBGA packages  
• JTAG boundary scan for BGA and fBGA packages  
• “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
The CY7C1381C/CY7C1383C operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
133 MHz  
117 MHz  
7.5  
100 MHz  
8.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
6.5  
210  
70  
190  
70  
175  
70  
Maximum CMOS Standby Current  
1
2
3
4
5
6
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.  
3,  
2
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05238 Rev. *B  
Revised February 26, 2004  
1234567...36

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