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CY7C1380C-167BGI PDF预览

CY7C1380C-167BGI

更新时间： 2024-11-23 22:38:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
36页 793K
描述
18-Mb (512K x 36/1M x 18) Pipelined SRAM

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中文翻译

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CY7C1380C-167BGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.81最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：167 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.07 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.275 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1380C-167BGI 数据手册

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CY7C1380C  
CY7C1382C  
18-Mb (512K x 36/1M x 18) Pipelined SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
• Available speed grades are 250, 225, 200,166 and  
133MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
• 2.5V / 3.3V I/O operation  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 2.8 ns (for 225-MHz device)  
— 3.0 ns (for 200-MHz device)  
The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36  
and 1,048,576 x 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining Chip Enable (  
), depth-expansion Chip  
CE1  
Enables (CE and  
[2]), Burst Control inputs (  
,
,
CE3  
), Write Enables (  
2
ADSC ADSP  
, and  
BWX  
), and Global Write  
and  
ADV  
BWE  
(
). Asynchronous inputs include the Output Enable (  
)
OE  
GW  
and the ZZ pin.  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor ( ) or  
— 3.4 ns (for 166-MHz device)  
— 4.2 ns (for 133-MHz device)  
ADSP  
) are active. Subsequent  
Address Strobe Controller (  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
ADV  
Pentium interleaved or linear burst sequences  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
controlled by the byte write control inputs.  
when active  
GW  
• Single Cycle Chip Deselect  
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA  
and 165-Ball fBGA packages  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
causes all bytes to be written.  
LOW  
The CY7C1380C/CY7C1382C operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
250 MHz  
225 MHz  
2.8  
200 MHz  
3.0  
167 MHz  
3.4  
133 MHz  
4.2  
Unit  
ns  
Maximum Access Time  
2.6  
350  
70  
Maximum Operating Current  
325  
300  
275  
245  
mA  
mA  
Maximum CMOS Standby Current  
Shaded areas contain advance information.  
70  
70  
70  
70  
Please contact your local Cypress sales representative for availability of these parts.  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.  
3
2
Cypress Semiconductor Corporation  
Document #: 38-05237 Rev. *D  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised February 26, 2004  
1234567...36

中文翻译

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