Datasheet > 存储 > SRAM> CY7C1380CV25-167BGC

CY7C1380CV25-167BGC

更新时间： 2024-11-27 04:01:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
33页	511K
描述
18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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CY7C1380CV25

CY7C1382CV25

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1380CV25/CY7C1382CV25 SRAM integrates

524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

• Available speed grades are 250, 225, 200,166 and

133 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

• Fast clock-to-output times

inputs, address-pipelining Chip Enable

(

), depth-

CE₁

[2]

expansion Chip Enables (CE₂and

), Burst Control

CE₃

— 2.6 ns (for 250-MHz device)

inputs ( ,

and

ADSC ADSP

), Write Enables ( , and

ADV

BW_X

— 2.8 ns (for 225-MHz device)

), and Global Write (

BWE

). Asynchronous inputs include

— 3.0 ns (for 200-MHz device)

the Output Enable ( ) and the ZZ pin.

— 3.4 ns (for 166-MHz device)

Addresses and chip enables are registered at rising edge of

— 4.2 ns (for 133-MHz device)

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

• Provide high-performance 3-1-1-1 access rate

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• User-selectable burst counter supporting Intel^

Pentium interleaved or linear burst sequences

ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

controlled by the byte write control inputs.

when active

• Single Cycle Chip Deselect

causes all bytes to be written.

LOW

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

The CY7C1380CV25/CY7C1382CV25 operates from a +2.5V

core power supply. All outputs also operate with a +2.5 supply.

All inputs and outputs are JEDEC-standard JESD8-5-

compatible.

and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Selection Guide

250 MHz

225 MHz

2.8

200 MHz

3.0

167 MHz

3.4

133 MHz

4.2

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

2.6

350

325

300

275

245

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE , CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05240 Rev. *C

Revised May 11, 2004

12 3 4 5 6 7...33

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与CY7C1380CV25-167BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1380CV25-167BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25-167BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25-167BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25-200AC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25-200AI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM
CY7C1380CV25-200BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25-200BGI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM
CY7C1380CV25-200BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1380CV25-200BZI	CYPRESS	获取价格	512K x 36/1M x 18 Pipelined SRAM
CY7C1380CV25-225AC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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