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CY7C1372CV25-250BGI PDF预览

CY7C1372CV25-250BGI

更新时间： 2024-11-07 21:59:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
27页 687K
描述
512K x 36/1M x 18 Pipelined SRAM with NoBL⑩ Architecture

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CY7C1372CV25-250BGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.79最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：18功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.06 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.35 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1372CV25-250BGI 数据手册

 浏览型号CY7C1372CV25-250BGI的Datasheet PDF文件第2页浏览型号CY7C1372CV25-250BGI的Datasheet PDF文件第3页浏览型号CY7C1372CV25-250BGI的Datasheet PDF文件第4页浏览型号CY7C1372CV25-250BGI的Datasheet PDF文件第5页浏览型号CY7C1372CV25-250BGI的Datasheet PDF文件第6页浏览型号CY7C1372CV25-250BGI的Datasheet PDF文件第7页 
CY7C1370CV25  
CY7C1372CV25  
512K x 36/1M x 18 Pipelined SRAM  
with NoBL™ Architecture  
Functional Description  
Features  
• Pin-compatible and functionally equivalent to ZBT™  
• Supports 250-MHz bus operations with zero wait states  
The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x  
36 and 1M x 18 Synchronous pipelined burst SRAMs with No  
Bus Latency™ (NoBL) logic, respectively. They are  
designed to support unlimited true back-to-back Read/Write  
operations with no wait states. The CY7C1370CV25 and  
CY7C1372CV25 are equipped with the advanced (NoBL) logic  
required to enable consecutive Read/Write operations with  
data being transferred on every clock cycle. This feature  
dramatically improves the throughput of data in systems that  
require frequent Write/Read transitions. The CY7C1370CV25  
and CY7C1372CV25 are pin compatible and functionally  
equivalent to ZBT devices.  
— Available speed grades are 250, 225, 200 and 167  
MHz  
• Internally self-timed output buffer control to eliminate  
the need to use asynchronous OE  
• Fully registered (inputs and outputs) for pipelined  
operation  
• Byte Write capability  
• Single 2.5V power supply  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 2.8 ns (for 225-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.4 ns (for 167-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. The  
clock input is qualified by the Clock Enable (CEN) signal,  
which when deasserted suspends operation and extends the  
previous clock cycle.  
Write operations are controlled by the Byte Write Selects  
(BWa–BWd for CY7C1370CV25 and BWa–BWb for  
CY7C1372CV25) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
• Available in 100 TQFP, 119 BGA, and 165 fBGA  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
packages  
• IEEE 1149.1 JTAG Boundary Scan  
• Burst capability—linear or interleaved burst order  
• “ZZ” Sleep Mode option and Stop Clock option  
Logic Block Diagram–CY7C1370CV25 (512K x 36)  
ADDRESS  
REGISTER 0  
A0, A1, A  
A1  
A0  
A1'  
A0'  
D1  
D0  
Q1  
Q0  
BURST  
LOGIC  
MODE  
C
ADV/LD  
C
CLK  
CEN  
WRITE ADDRESS  
REGISTER 1  
WRITE ADDRESS  
REGISTER 2  
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD  
A
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
R
E
G
I
MEMORY  
ARRAY  
B
U
F
S
T
E
E
R
I
DQs  
DQP  
DQP  
DQP  
DQP  
WRITE  
DRIVERS  
BW  
BW  
a
a
b
c
d
A
M
P
b
BW  
BW  
c
S
T
E
R
S
F
d
E
R
S
S
WE  
E
E
N
G
INPUT  
REGISTER 1  
INPUT  
REGISTER 0  
E
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05235 Rev. *C  
Revised June 03, 2004  
1234567...27

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