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CY7C1360V25-133BGC PDF预览

CY7C1360V25-133BGC

更新时间: 2024-11-24 14:41:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
31页 1126K
描述
Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

CY7C1360V25-133BGC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
针数:119Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.75最长访问时间:4.2 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:9437184 bit内存集成电路类型:CACHE SRAM
内存宽度:36功能数量:1
端子数量:119字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5 V
认证状态:Not Qualified座面最大高度:2.4 mm
最大待机电流:0.01 A最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.35 mA
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

CY7C1360V25-133BGC 数据手册

 浏览型号CY7C1360V25-133BGC的Datasheet PDF文件第2页浏览型号CY7C1360V25-133BGC的Datasheet PDF文件第3页浏览型号CY7C1360V25-133BGC的Datasheet PDF文件第4页浏览型号CY7C1360V25-133BGC的Datasheet PDF文件第5页浏览型号CY7C1360V25-133BGC的Datasheet PDF文件第6页浏览型号CY7C1360V25-133BGC的Datasheet PDF文件第7页 
329  
CY7C1360V25  
CY7C1362V25  
CY7C1364V25  
PRELIMINARY  
256K x 36/256K x 32/512K x 18 Pipelined SRAM  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock. Max-  
Features  
• Supports 200-MHz bus  
imum access delay from the clock rise is 3.1 ns (200-MHz  
device).  
• Fully registered inputs and outputs for pipelined  
operation  
• Single 2.5V power supply  
• Fast clock-to-output times  
— 3.1 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device  
— 5.0 ns (for 100-MHz device  
The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports  
either the interleaved burst sequence used by the Intel Pen-  
tium processor or a linear burst sequence used by processors  
such as the PowerPC™. The burst sequence is selected  
through the MODE pin. Accesses can be initiated by assert-  
ing either the Processor Address Strobe (ADSP) or the Con-  
troller Address Strobe (ADSC) at clock rise. Address advance-  
ment through the burst sequence is controlled by the ADV  
input. A 2-bit on-chip wraparound burst counter captures the  
first address in a burst sequence and automatically increments  
the address for the rest of the burst access.  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
• Available as a 100-pin TQFP or 119 BGA  
• “ZZ” Sleep Mode option and Stop Clock option  
Byte write operations are qualified with the Byte Write Select  
(BWa,b,c,d for 1360V25/1364V25 and BWa,b for 1362V25) in-  
puts. A Global Write Enable (GW) overrides all byte write in-  
puts and writes data to all four bytes. All writes are conducted  
with on-chip synchronous self-timed write circuitry.  
Functional Description  
Three synchronous Chip Selects (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank se-  
lection and output three-state control. In order to provide prop-  
er data during depth expansion, OE is masked during the first  
clock of a read cycle when emerging from a deselected state.  
The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are  
2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-pipe-  
lined cache SRAM, respectively. They are designed to support  
zero wait state secondary cache with minimal glue logic.  
Logic Block Diagram  
D
CLK  
Data-In REG.  
CE  
Q
ADV  
A
x
GW  
CE  
CONTROL  
and WRITE  
LOGIC  
256Kx36/  
512Kx18  
1
CE  
CE  
2
DQ  
DP  
x
x
MEMORY  
ARRAY  
3
BWE  
BW  
x
MODE  
ADSP  
ADSC  
ZZ  
OE  
1360V25  
1362V25  
1364V25  
A
A
A
[17:0]  
A
[18:0]  
X
[18:0]  
DQ  
DQ  
DP  
DQ  
a,b  
a,b,c,d  
DQ  
DP  
a,b  
X
DP  
NC  
a,b,c,d  
a,b  
X
BW  
BW  
BW  
a,b,c,d  
BW  
a,b  
X
a,b  
Intel and Pentium are registered trademarks of Intel Corporation.  
PowerPC is a trademark of IBM Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
October 20, 2000  

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