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CY7C1361A-117AJC PDF预览

CY7C1361A-117AJC

更新时间： 2024-11-27 03:05:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
26页 818K
描述
256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM

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中文翻译

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CY7C1361A-117AJC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.74Is Samacsys：N
最长访问时间：7.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：117 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：9437184 bit
内存集成电路类型：STANDARD SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.01 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.41 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

CY7C1361A-117AJC 数据手册

 浏览型号CY7C1361A-117AJC的Datasheet PDF文件第2页浏览型号CY7C1361A-117AJC的Datasheet PDF文件第3页浏览型号CY7C1361A-117AJC的Datasheet PDF文件第4页浏览型号CY7C1361A-117AJC的Datasheet PDF文件第5页浏览型号CY7C1361A-117AJC的Datasheet PDF文件第6页浏览型号CY7C1361A-117AJC的Datasheet PDF文件第7页 
CY7C1361A  
CY7C1363A  
256K x 36/512K x 18 Synchronous  
Flow-Thru Burst SRAM  
synchronous peripheral circuitry and a two-bit counter for  
internal burst operation. All synchronous inputs are gated by  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enable (CE), depth-expansion  
Chip Enables (CE2 and CE2), burst control inputs (ADSC,  
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and  
BWE), and global Write (GW). However, the CE2 chip enable  
input is only available for the TA package version.  
Features  
• Fast access times: 6.0, 6.5, 7.0, and 8.0ns  
• Fast clock speed: 150, 133, 117, and 100MHz  
• Fast OE access times: 3.5 ns and 4.0 ns  
• Optimal for depth expansion (one cycle chip deselect  
to eliminate bus contention)  
• 3.3V –5% and +10% power supply  
• 3.3V or 2.5V I/O supply  
• 5V tolerant inputs except I/Os  
• Clamp diodes to VSS at all inputs and outputs  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Multiple chip enables for depth expansion: A package  
version and two chip enables for BG and AJ package  
versions  
Asynchronous inputs include the Output Enable (OE) and  
burst mode control (MODE). The data outputs (Q), enabled by  
OE, are also asynchronous.  
Addresses and chip enables are registered with either  
Address Status Processor (ADSP) or Address Status  
Controller (ADSC) input pins. Subsequent burst addresses  
can be internally generated as controlled by the Burst Advance  
Pin (ADV).  
• Address pipeline capability  
• Address, data, and control registers  
• Internally self-timed Write cycle  
• Burst control pins (interleaved or linear burst  
sequence)  
• Automatic power-down feature available using ZZ  
mode or CE deselect.  
• JTAG boundary scan for BG and AJ package version  
• Low-profile 119-bump 14-mm × 22-mm PBGA (Ball Grid  
Array) and 100-pin TQFP packages  
Address, data inputs, and Write controls are registered on-chip  
to initiate self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the Write control inputs.  
Individual byte Write allows individual byte to be written. BWa  
controls DQa. BWb controls DQb. BWc controls DQc. BWd  
controls DQd. BWa, BWb, BWc, and BWd can be active only  
with BWE being LOW. GW being LOW causes all bytes to be  
written. The x18 version only has 18 data inputs/outputs (DQa  
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and  
DQd).  
For the B and T package versions, four pins are used to  
implement JTAG test capabilities: Test Mode Select (TMS),  
Test Data-In (TDI), Test Clock (TCK), and Test Data-Out  
(TDO). The JTAG circuitry is used to serially shift data to and  
from the device. JTAG inputs use LVTTL/LVCMOS levels to  
shift data during this testing mode of operation. The TA  
package version does not offer the JTAG capability.  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced  
triple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high-valued  
resistors.  
The CY7C1361A and CY7C1363A operate from a +3.3V  
power supply. All inputs and outputs are LVTTL-compatible.  
The CY7C1361A and CY7C1363A SRAMs integrate 262,144  
× 36 and 524,288 × 18 SRAM cells with advanced  
Selection Guide  
7C1361A-150  
7C1363A-150  
7C1361A-133  
7C1363A-133  
7C1361A-117  
7C1363A-117  
7C1361A-100  
7C1363A-100  
Unit  
ns  
Maximum Access Time  
6.0  
480  
10  
6.5  
360  
10  
7.0  
320  
10  
8.0  
270  
10  
Maximum Operating Current  
Maximum CMOS Standby Current  
mA  
mA  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05259 Rev. *A  
Revised June 19, 2002  
1234567...26

中文翻译

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与CY7C1361A-117AJC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1361A-117AJCT CYPRESS

获取价格

 		Standard SRAM, 256KX36, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1361A-117AJI CYPRESS

获取价格

 		256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1361A-117AJIT CYPRESS

获取价格

 		Standard SRAM, 256KX36, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1361A-117BGC CYPRESS

获取价格

 		256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1361A-117BGCT CYPRESS

获取价格

 		Standard SRAM, 256KX36, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1361A-117BGI CYPRESS

获取价格

 		256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1361A-117BGI ROCHESTER

获取价格

 		256KX36 STANDARD SRAM, 7.5ns, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1361A-117BGIT CYPRESS

获取价格

 		Standard SRAM, 256KX36, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1361A-133AC CYPRESS

获取价格

 		256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1361A-133ACT CYPRESS

获取价格

 		Standard SRAM, 256KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10

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