Datasheet > CY7C1315KV18-250BZCT

CY7C1315KV18-250BZCT

更新时间： 2024-11-16 19:47:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
33页	635K
描述
Standard SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165

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CY7C1315KV18-250BZCT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	包装说明：	LBGA, BGA165,11X15,40
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.4
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	235	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.25 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.59 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm
Base Number Matches：	1

CY7C1315KV18-250BZCT 数据手册

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CY7C1311KV18/CY7C1911KV18

CY7C1313KV18/CY7C1315KV18



18-Mbit QDR^®II SRAM

Four-Word Burst Architecture

18-Mbit QDR^®II SRAM Four-Word Burst Architecture

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

CY7C1311KV18 – 2M × 8

CY7C1911KV18 – 2M × 9

CY7C1313KV18 – 1M × 18

CY7C1315KV18 – 512K × 36

■ 333-MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 666 MHz) at 333 MHz

Functional Description

The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and

CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs,

equipped with QDR II architecture. QDR II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR II architecture has

separate data inputs and data outputs to completely eliminate

the need to ‘turnaround’ the data bus that exists with common

I/O devices. Each port can be accessed through a common

address bus. Addresses for read and write addresses are

latched on alternate rising edges of the input (K) clock. Accesses

to the QDR II read and write ports are independent of one

another. To maximize data throughput, both read and write ports

are equipped with DDR interfaces. Each address location is

associated with four 8-bit words (CY7C1311KV18), 9-bit words

(CY7C1911KV18), 18-bit words (CY7C1313KV18), or 36-bit

words (CY7C1315KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus ‘turnarounds’.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

■ Available in × 8, × 9, × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Core V_DD= 1.8 V (±0.1 V); I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-ball FBGA package (13 × 15 ×1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ PLL for accurate data placement

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum operating frequency

333 MHz

300 MHz

250 MHz Unit

333

300

250

430

440

590

MHz

Maximum operating current

× 8 Not Offered Not Offered

× 9

520

530

730

490

500

670

× 18

× 36

Cypress Semiconductor Corporation

Document Number: 001-58904 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 1, 2017

12 3 4 5 6 7...33

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CY7C1315KV18-250BZCT 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1315KV18-250BZXC	CYPRESS	完全替代	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZC	CYPRESS	完全替代	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite

与CY7C1315KV18-250BZCT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1315KV18-250BZI	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZI_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZXC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1315KV18-250BZXC_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZXI	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZXI_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-300BZC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-300BZC_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-300BZXC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite

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