Datasheet > CY7C1315KV18-250BZI_12

CY7C1315KV18-250BZI_12

更新时间： 2024-11-16 12:23:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	1365K
描述
18-Mbit QDRÂ® II SRAM Four-Word Burst Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1315KV18-250BZI_12 数据手册

浏览型号CY7C1315KV18-250BZI_12的Datasheet PDF文件第2页

浏览型号CY7C1315KV18-250BZI_12的Datasheet PDF文件第3页

浏览型号CY7C1315KV18-250BZI_12的Datasheet PDF文件第4页

浏览型号CY7C1315KV18-250BZI_12的Datasheet PDF文件第5页

浏览型号CY7C1315KV18-250BZI_12的Datasheet PDF文件第6页

浏览型号CY7C1315KV18-250BZI_12的Datasheet PDF文件第7页

CY7C1311KV18, CY7C1911KV18

CY7C1313KV18, CY7C1315KV18



18-Mbit QDR^®II SRAM

Four-Word Burst Architecture

18-Mbit QDR^®II SRAM Four-Word Burst Architecture

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

CY7C1311KV18 – 2 M × 8

CY7C1911KV18 – 2 M × 9

CY7C1313KV18 – 1 M × 18

CY7C1315KV18 – 512 K × 36

■ 333-MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 666 MHz) at 333 MHz

Functional Description

The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and

CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs,

equipped with QDR II architecture. QDR II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR II architecture has

separate data inputs and data outputs to completely eliminate

the need to ‘turnaround’ the data bus that exists with common

I/O devices. Each port can be accessed through a common

address bus. Addresses for read and write addresses are

latched on alternate rising edges of the input (K) clock. Accesses

to the QDR II read and write ports are independent of one

another. To maximize data throughput, both read and write ports

are equipped with DDR interfaces. Each address location is

associated with four 8-bit words (CY7C1311KV18), 9-bit words

(CY7C1911KV18), 18-bit words (CY7C1313KV18), or 36-bit

words (CY7C1315KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus ‘turnarounds’.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

■ OperatessimilartoQDRIdevicewith1cyclereadlatencywhen

DOFF is asserted LOW

■ Available in × 8, × 9, × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ Core V_DD= 1.8 V (±0.1 V); I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Available in 165-ball FBGA package (13 × 15 ×1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ PLL for accurate data placement

Selection Guide

Description

Maximum operating frequency

333 MHz

300 MHz

250 MHz Unit

333

300

250

430

440

590

MHz

Maximum operating current

× 8 Not Offered Not Offered

× 9

520

530

730

490

500

670

× 18

× 36

Cypress Semiconductor Corporation

Document Number: 001-58904 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 23, 2012

12 3 4 5 6 7...32

中文翻译

下载PDF

与CY7C1315KV18-250BZI_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C1315KV18-250BZXC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZXC	INFINEON	获取价格	Synchronous SRAM
CY7C1315KV18-250BZXC_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZXI	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-250BZXI_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-300BZC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-300BZC_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-300BZXC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-300BZXC_12	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite
CY7C1315KV18-333BZC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite

与CY7C1315KV18-250BZI_12相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

14
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

8
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

36
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1315KV18-250BZI_12

CY7C1315KV18-250BZI_12 数据手册

与CY7C1315KV18-250BZI_12相关器件

与CY7C1315KV18-250BZI_12相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1315KV18-250BZI_12

CY7C1315KV18-250BZI_12 数据手册

与CY7C1315KV18-250BZI_12相关器件

与CY7C1315KV18-250BZI_12相关文章

您还可以找

您在本页遇到什么问题？