Datasheet > CY7C1161V18-400BZC

CY7C1161V18-400BZC

更新时间： 2024-11-24 08:50:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	659K
描述
QDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1161V18-400BZC 数据手册

浏览型号CY7C1161V18-400BZC的Datasheet PDF文件第2页

浏览型号CY7C1161V18-400BZC的Datasheet PDF文件第3页

浏览型号CY7C1161V18-400BZC的Datasheet PDF文件第4页

浏览型号CY7C1161V18-400BZC的Datasheet PDF文件第5页

浏览型号CY7C1161V18-400BZC的Datasheet PDF文件第6页

浏览型号CY7C1161V18-400BZC的Datasheet PDF文件第7页

CY7C1161V18, CY7C1176V18

CY7C1163V18, CY7C1165V18

18-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

Features

Functional Description

■ Separate independent read and write data ports

❐ Supports concurrent transactions

The CY7C1161V18, CY7C1176V18, CY7C1163V18, and

CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs

equipped with QDR™-II+ architecture. QDR-II+ architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

■ 300 MHz to 400 MHz clock for high bandwidth

■ 4-word burst to reduce address bus frequency

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 800 MHz) at 400 MHz

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to turn around the

data bus that is required with common IO devices. Each port can

be accessed through a common address bus. Addresses for

read and write addresses are latched onto alternate rising edges

of the input (K) clock. Accesses to the QDR-II+ read and write

ports are completely independent of one another. In order to

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words

(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks K and K, memory bandwidth is maximized while simpli-

fying system design by eliminating bus turnarounds.

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

Depth expansion is accomplished with port selects for each port.

Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the or K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With cycle read latency of 2.5 cycles:

CY7C1161V18 – 2M x 8

CY7C1176V18 – 2M x 9

CY7C1163V18 – 1M x 18

CY7C1165V18 – 512K x 36

Selection Guide

Description

400 MHz

400

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

1080

1020

920

850

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06582 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 06, 2008

[+] Feedback

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1161V18-400BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1161V18-400BZI	CYPRESS	获取价格	QDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
CY7C1161V18-400BZXI	CYPRESS	获取价格	QDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBG
CY7C11631KV18	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1163KV18	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1163KV18-400BZI	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1163KV18-400BZI	INFINEON	获取价格	Synchronous SRAM
CY7C1163KV18-450BZC	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1163KV18-550BZC	CYPRESS	获取价格	18-Mbit QDR? II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1163KV18-550BZC	INFINEON	获取价格	Synchronous SRAM
CY7C1163V18	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu

与CY7C1161V18-400BZC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

36
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

28
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

56
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

53

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1161V18-400BZC

CY7C1161V18-400BZC 数据手册

与CY7C1161V18-400BZC相关器件

与CY7C1161V18-400BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1161V18-400BZC

CY7C1161V18-400BZC 数据手册

与CY7C1161V18-400BZC相关器件

与CY7C1161V18-400BZC相关文章

您还可以找

您在本页遇到什么问题？