Datasheet > CY7C1156V18

CY7C1156V18

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	1159K
描述
18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

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CY7C1156V18 数据手册

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Pin Definitions (continued)

Pin Name

Pin Description

Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 23.

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

bus impedance. CQ, CQ and Q_[x:0]output impedance are set to 0.2 x RQ, where RQ is a resistor

connected between ZQ and ground. Alternatively, connect this pin directly to V_DDQ, which enables

the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The

timings in the DLL turned off operationis different from those listed in this data sheet. For normal

operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves

in QDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to

167 MHz with QDR-I timing.

TDO

Output

Input

N/A

TDO for JTAG.

TCK

TCK pin for JTAG.

TDI

TDI pin for JTAG.

TMS

TMS pin for JTAG.

Not connected to the die. Tie to any voltage level.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and

NC/36M

NC/72M

NC/144M

NC/288M

V_REF

N/A

Input-

Reference AC measurement points.

V_DD

V_SS

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the device.

V_DDQ

Power Supply Power supply inputs for the outputs of the device.

Document Number: 001-06583 Rev. *C

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