Datasheet > CY7C1143KV18-450BZC

CY7C1143KV18-450BZC

更新时间： 2024-11-09 12:22:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	619K
描述
18-Mbit QDRÂ® II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1143KV18-450BZC 技术参数

是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	2.3	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	450 MHz
I/O 类型：	SEPARATE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	QDR SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	235
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大待机电流：	0.31 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.67 mA	最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	13 mm	Base Number Matches：	1

CY7C1143KV18-450BZC 数据手册

浏览型号CY7C1143KV18-450BZC的Datasheet PDF文件第2页

浏览型号CY7C1143KV18-450BZC的Datasheet PDF文件第3页

浏览型号CY7C1143KV18-450BZC的Datasheet PDF文件第4页

浏览型号CY7C1143KV18-450BZC的Datasheet PDF文件第5页

浏览型号CY7C1143KV18-450BZC的Datasheet PDF文件第6页

浏览型号CY7C1143KV18-450BZC的Datasheet PDF文件第7页



CY7C1143KV18, CY7C1145KV18

18-Mbit QDR^®II+ SRAM Four-Word Burst

Architecture (2.0 Cycle Read Latency)

18-Mbit QDR^®II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

Features

Configurations

■ Separate independent read and write data ports

❐ Supports concurrent transactions

With Read Cycle Latency of 2.0 cycles:

CY7C1143KV18 – 1 M × 18

■ 450-MHz clock for high bandwidth

CY7C1145KV18 – 512 K × 36

■ Four-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) Interfaces on both read and write ports

(data transferred at 900 MHz) at 450 MHz

The CY7C1143KV18, and CY7C1145KV18 are 1.8

Synchronous Pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turnaround” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ read and write ports are completely

independent of one another. To maximize data throughput, both

read and write ports are equipped with DDR interfaces. Each

address location is associated with four 18-bit words

(CY7C1143KV18), or 36-bit words (CY7C1145KV18) that burst

sequentially into or out of the device. Because data is transferred

into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus ‘turnarounds’.

■ Available in 2.0 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR^®II+ operates with 2.0 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to QDR I device with one cycle read latency

when DOFF is asserted LOW

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

[1]

■ Core V_DD= 1.8 V± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

450 MHz

450

400 MHz Unit

400

610

850

MHz

Maximum operating current

× 18

× 36

670

930

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-58910 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 5, 2012

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1143KV18-450BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1143V18	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1143V18-300BZC	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1143V18-300BZI	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1143V18-300BZXC	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1143V18-300BZXI	CYPRESS	获取价格	18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architectu
CY7C1143V18-333BZC	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
CY7C1143V18-333BZI	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
CY7C1143V18-333BZXC	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPB
CY7C1143V18-375BZI	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
CY7C1145KV18-400BZXC	CYPRESS	获取价格	18-Mbit QDRÂ® II SRAM Four-Word Burst Archite

与CY7C1143KV18-450BZC相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1143KV18-450BZC

CY7C1143KV18-450BZC 技术参数

CY7C1143KV18-450BZC 数据手册

与CY7C1143KV18-450BZC相关器件

与CY7C1143KV18-450BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1143KV18-450BZC

CY7C1143KV18-450BZC 技术参数

CY7C1143KV18-450BZC 数据手册

与CY7C1143KV18-450BZC相关器件

与CY7C1143KV18-450BZC相关文章

您还可以找

您在本页遇到什么问题？